| |
 |
|
Class Information
Number: 708/507
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Parallel
Description: Subject matter wherein the operation is effected by the use of two or more processors running simultaneously.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7627802 |
Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications |
Dec. 1, 2009 |
| 7120248 |
Multiple prime number generation using a parallel prime number search algorithm |
Oct. 10, 2006 |
| 6637002 |
Decoder for error correcting block codes |
Oct. 21, 2003 |
| 6570670 |
Method and apparatus to enable job streaming for a set of commonly shared resources |
May. 27, 2003 |
| 6401194 |
Execution unit for processing a data stream independently and in parallel |
Jun. 4, 2002 |
| 6327605 |
Data processor and data processing system |
Dec. 4, 2001 |
| 6243732 |
Data processor and data processing system |
Jun. 5, 2001 |
| 6038582 |
Data processor and data processing system |
Mar. 14, 2000 |
| 5963461 |
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization |
Oct. 5, 1999 |
| 5896543 |
Digital signal processor architecture |
Apr. 20, 1999 |
| 5764556 |
Method and apparatus for performing floating point addition |
Jun. 9, 1998 |
| 5602768 |
Method and apparatus for reducing the processing time required to solve square root problems |
Feb. 11, 1997 |
| 5339266 |
Parallel method and apparatus for detecting and completing floating point operations involving special operands |
Aug. 16, 1994 |
| 5268855 |
Common format for encoding both single and double precision floating point numbers |
Dec. 7, 1993 |
| 5267186 |
Normalizing pipelined floating point processing unit |
Nov. 30, 1993 |
| 5136536 |
Floating-point ALU with parallel paths |
Aug. 4, 1992 |
| 5058048 |
Normalizing pipelined floating point processing unit |
Oct. 15, 1991 |
| 4943940 |
Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus |
Jul. 24, 1990 |
| 4916651 |
Floating point processor architecture |
Apr. 10, 1990 |
| 4901235 |
Data processing system having unique multilevel microcode architecture |
Feb. 13, 1990 |
| 4888682 |
Parallel vector processor using multiple dedicated processors and vector registers divided into smaller registers |
Dec. 19, 1989 |
| 4884190 |
High performance parallel vector processor having a modified vector register/element processor configuration |
Nov. 28, 1989 |
| 4766564 |
Dual putaway/bypass busses for multiple arithmetic units |
Aug. 23, 1988 |
| 4683547 |
Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance |
Jul. 28, 1987 |
| 4612628 |
Floating-point unit constructed of identical modules |
Sep. 16, 1986 |
| 4488252 |
Floating point addition architecture |
Dec. 11, 1984 |
| 4429370 |
Arithmetic unit for use in a data processing system for computing exponent results and detecting overflow and underflow conditions thereof |
Jan. 31, 1984 |
| 4075704 |
Floating point data processor for high speech operation |
Feb. 21, 1978 |
|
|
|
