 |
|
 |
| |
 |
|
Class Information
Number: 708/505
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Addition or subtraction
Description: Subject matter wherein the operation performed is addition or subtraction.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617268 |
Method and apparatus supporting non-additive calculations in graphics accelerators and digital signal processors |
Nov. 10, 2009 |
| 7592835 |
Co-processor having configurable logic blocks |
Sep. 22, 2009 |
| 7574584 |
Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine |
Aug. 11, 2009 |
| 7552165 |
Method and system to implement an improved floating point adder with integrated adding and rounding |
Jun. 23, 2009 |
| 7546328 |
Decimal floating-point adder |
Jun. 9, 2009 |
| 7519645 |
System and method for performing decimal floating point addition |
Apr. 14, 2009 |
| 7490119 |
High speed adder design for a multiply-add based floating point unit |
Feb. 10, 2009 |
| 7475104 |
System and method for providing a double adder for decimal floating point operations |
Jan. 6, 2009 |
| 7469265 |
Methods and apparatus for performing multi-value range checks |
Dec. 23, 2008 |
| 7437400 |
Data processing apparatus and method for performing floating point addition |
Oct. 14, 2008 |
| 7433911 |
Data processing apparatus and method for performing floating point addition |
Oct. 7, 2008 |
| 7392274 |
Multi-function floating point arithmetic pipeline |
Jun. 24, 2008 |
| 7373369 |
Advanced execution of extended floating-point add operations in a narrow dataflow |
May. 13, 2008 |
| 7366749 |
Floating point adder with embedded status information |
Apr. 29, 2008 |
| 7356553 |
Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements |
Apr. 8, 2008 |
| 7356554 |
Variable fixed multipliers using memory blocks |
Apr. 8, 2008 |
| 7346644 |
Devices and methods with programmable logic and digital signal processing regions |
Mar. 18, 2008 |
| 7322032 |
Methods and apparatus for scheduling operation of a data source |
Jan. 22, 2008 |
| 7164290 |
Field programmable gate array logic unit and its cluster |
Jan. 16, 2007 |
| 7119576 |
Devices and methods with programmable logic and digital signal processing regions |
Oct. 10, 2006 |
| 7099910 |
Partitioned shifter for single instruction stream multiple data stream (SIMD) operations |
Aug. 29, 2006 |
| 7061268 |
Initializing a carry chain in a programmable logic device |
Jun. 13, 2006 |
| 7043516 |
Reduction of add-pipe logic by operand offset shift |
May. 9, 2006 |
| 7027598 |
Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 7027597 |
Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 7024439 |
Leading Zero Anticipatory (LZA) algorithm and logic for high speed arithmetic units |
Apr. 4, 2006 |
| 6988115 |
Method and apparatus to correct leading one prediction |
Jan. 17, 2006 |
| 6988119 |
Fast single precision floating point accumulator using base 32 system |
Jan. 17, 2006 |
| 6963896 |
Method and system to implement an improved floating point adder with integrated adding and rounding |
Nov. 8, 2005 |
| 6943579 |
Variable fixed multipliers using memory blocks |
Sep. 13, 2005 |
| 6941335 |
Random carry-in for floating-point operations |
Sep. 6, 2005 |
| 6895424 |
Method and circuit for alignment of floating point significants in a SIMD array MPP |
May. 17, 2005 |
| 6889241 |
Floating point adder |
May. 3, 2005 |
| 6857061 |
Method and apparatus for obtaining a scalar value directly from a vector register |
Feb. 15, 2005 |
| 6836147 |
Function block |
Dec. 28, 2004 |
| 6785701 |
Apparatus and method of performing addition and rounding operation in parallel for floating-point arithmetic logical unit |
Aug. 31, 2004 |
| 6771094 |
Devices and methods with programmable logic and digital signal processing regions |
Aug. 3, 2004 |
| 6757812 |
Leading bit prediction with in-parallel correction |
Jun. 29, 2004 |
| 6754688 |
Method and apparatus to calculate the difference of two numbers |
Jun. 22, 2004 |
| 6754542 |
Control arithmetic apparatus and method |
Jun. 22, 2004 |
| 6731138 |
Circuits and methods for selectively latching the output of an adder |
May. 4, 2004 |
| 6721773 |
Single precision array processor |
Apr. 13, 2004 |
| 6668268 |
Method and apparatus for compiling dependent subtraction operations on arithmetic intervals |
Dec. 23, 2003 |
| 6631392 |
Method and apparatus for predicting floating-point exceptions |
Oct. 7, 2003 |
| 6581087 |
Floating point adder capable of rapid clip-code generation |
Jun. 17, 2003 |
| 6578060 |
Floating-point calculation apparatus |
Jun. 10, 2003 |
| 6571267 |
Floating point addition/subtraction execution unit |
May. 27, 2003 |
| 6557097 |
Linear vector computation |
Apr. 29, 2003 |
| 6538470 |
Devices and methods with programmable logic and digital signal processing regions |
Mar. 25, 2003 |
| 6529924 |
Method and apparatus for generating shift amount signals for an alignment shifter |
Mar. 4, 2003 |
|
|
|
 |
|
 |
|
| |
Randomly Featured Patents |
|
