| Patent Number |
Title Of Patent |
Date Issued |
| 7609895 |
Methods and apparatus for performing MQ-decoding operations |
Oct. 27, 2009 |
| 7493357 |
Random carry-in for floating-point operations |
Feb. 17, 2009 |
| 7398289 |
Method and device for floating-point multiplication, and corresponding computer-program product |
Jul. 8, 2008 |
| 7330867 |
Method and device for floating-point multiplication, and corresponding computer-program product |
Feb. 12, 2008 |
| 7290024 |
Methods and apparatus for performing mathematical operations using scaled integers |
Oct. 30, 2007 |
| 7277540 |
Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography |
Oct. 2, 2007 |
| 7240204 |
Scalable and unified multiplication methods and apparatus |
Jul. 3, 2007 |
| 7219117 |
Methods and systems for computing floating-point intervals |
May. 15, 2007 |
| 7188133 |
Floating point number storage method and floating point arithmetic device |
Mar. 6, 2007 |
| 7113593 |
Recursive cryptoaccelerator and recursive VHDL design of logic circuits |
Sep. 26, 2006 |
| 7111166 |
Extending the range of computational fields of integers |
Sep. 19, 2006 |
| 7027597 |
Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 7027598 |
Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 7003540 |
Floating point multiplier for delimited operands |
Feb. 21, 2006 |
| 6988120 |
Arithmetic unit and method thereof |
Jan. 17, 2006 |
| 6922714 |
Floating point unit power reduction scheme |
Jul. 26, 2005 |
| 6901503 |
Data processing circuits and interfaces |
May. 31, 2005 |
| 6779013 |
Floating point overflow and sign detection |
Aug. 17, 2004 |
| 6697833 |
Floating-point multiplier for de-normalized inputs |
Feb. 24, 2004 |
| 6647404 |
Double precision floating point multiplier having a 32-bit booth-encoded array multiplier |
Nov. 11, 2003 |
| 6629120 |
Method and apparatus for performing a mask-driven interval multiplication operation |
Sep. 30, 2003 |
| 6606700 |
DSP with dual-mac processor and dual-mac coprocessor |
Aug. 12, 2003 |
| 6490607 |
Shared FP and SIMD 3D multiplier |
Dec. 3, 2002 |
| 6446104 |
Double precision floating point multiplier having a 32-bit booth-encoded array multiplier |
Sep. 3, 2002 |
| 6370247 |
Hash value generating method and device, data encryption method and device, data decryption method and device |
Apr. 9, 2002 |
| 6269385 |
Apparatus and method for performing rounding and addition in parallel in floating point multiplier |
Jul. 31, 2001 |
| 6269384 |
Method and apparatus for rounding and normalizing results within a multiplier |
Jul. 31, 2001 |
| 6233595 |
Fast multiplication of floating point values and integer powers of two |
May. 15, 2001 |
| 6226737 |
Apparatus and method for single precision multiplication |
May. 1, 2001 |
| 6205462 |
Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously |
Mar. 20, 2001 |
| 6175907 |
Apparatus and method for fast square root calculation within a microprocessor |
Jan. 16, 2001 |
| 6099158 |
Apparatus and methods for execution of computer instructions |
Aug. 8, 2000 |
| 6055554 |
Floating point binary quad word format multiply instruction unit |
Apr. 25, 2000 |
| 6032168 |
Computer system to perform a filter operation using a logarithm and inverse-logarithm converter and methods thereof |
Feb. 29, 2000 |
| 6026483 |
Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands |
Feb. 15, 2000 |
| 6021422 |
Partitioning of binary quad word format multiply instruction on S/390 processor |
Feb. 1, 2000 |
| 5999961 |
Parallel prefix operations in asynchronous processors |
Dec. 7, 1999 |
| 5991784 |
Signal processing circuit |
Nov. 23, 1999 |
| 5963461 |
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization |
Oct. 5, 1999 |
| 5909385 |
Multiplying method and apparatus |
Jun. 1, 1999 |
| 5844827 |
Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N |
Dec. 1, 1998 |
| 5841684 |
Method and apparatus for computer implemented constant multiplication with multipliers having repeated patterns including shifting of replicas and patterns having at least two digit positions |
Nov. 24, 1998 |
| 5790446 |
Floating point multiplier with reduced critical paths using delay matching techniques |
Aug. 4, 1998 |
| 5619439 |
Shared hardware for multiply, divide, and square root exponent calculation |
Apr. 8, 1997 |
| 5602769 |
Method and apparatus for partially supporting subnormal operands in floating point multiplication |
Feb. 11, 1997 |
| 5430668 |
Floating point multiplier capable of easily performing a failure detection test |
Jul. 4, 1995 |
| 5408426 |
Arithmetic unit capable of performing concurrent operations for high speed operation |
Apr. 18, 1995 |
| 5347481 |
Method and apparatus for multiplying denormalized binary floating point numbers without additional delay |
Sep. 13, 1994 |
| 5341319 |
Method and apparatus for controlling a rounding operation in a floating point multiplier circuit |
Aug. 23, 1994 |
| 5276634 |
Floating point data processing apparatus which simultaneously effects summation and rounding computations |
Jan. 4, 1994 |
