Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Information Technology
Class Information
Number: 708/501
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Multiplication followed by addition
Description: Subject matter wherein the operation performed is multiplication followed by an addition.










Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
8711146 Method and apparatuses for solving weighted planar graphs Apr. 29, 2014
8694572 Decimal floating-point fused multiply-add unit Apr. 8, 2014
8667042 Functional unit for vector integer multiply add instruction Mar. 4, 2014
8626813 Dual-path fused floating-point two-term dot product unit Jan. 7, 2014
8601047 Decimal floating-point adder with leading zero anticipation Dec. 3, 2013
8577948 Split path multiply accumulate unit Nov. 5, 2013
8549054 Arithmetic processing apparatus and arithmetic processing method Oct. 1, 2013
8495121 Arithmetic processing device and methods thereof Jul. 23, 2013
8489663 Decimal floating-point adder with leading zero anticipation Jul. 16, 2013
8471593 Logic cell array and bus system Jun. 25, 2013
8463834 Floating point multiplier with first and second partial product shifting circuitry for result alignment Jun. 11, 2013
8447800 Mode-based multiply-add recoding for denormal operands May. 21, 2013
8443032 Multiplication circuit and de/encryption circuit utilizing the same May. 14, 2013
8443030 Processing of floating point multiply-accumulate instructions using multiple operand pathways May. 14, 2013
8438208 Processor and method for implementing instruction support for multiplication of large operands May. 7, 2013
8429217 Executing fixed point divide operations using a floating point multiply-add pipeline Apr. 23, 2013
8423600 Accumulating operator and accumulating method for floating point operation Apr. 16, 2013
8402075 Mechanism for fast detection of overshift in a floating point unit of a processing device Mar. 19, 2013
8352533 Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable Jan. 8, 2013
8332453 Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result Dec. 11, 2012
8316071 Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor Nov. 20, 2012
8260837 Handling denormal floating point operands when result must be normalized Sep. 4, 2012
8239440 Processor which implements fused and unfused multiply-add instructions in a pipelined manner Aug. 7, 2012
8180822 Method and system for processing the booth encoding 33.sup.RD term May. 15, 2012
8166085 Reducing the latency of sum-addressed shifters Apr. 24, 2012
8166091 Floating-point fused dot-product unit Apr. 24, 2012
8131795 High speed adder design for a multiply-add based floating point unit Mar. 6, 2012
8090758 Enhanced multiplier-accumulator logic for a programmable logic device Jan. 3, 2012
8078660 Bridge fused multiply-adder circuit Dec. 13, 2011
8069200 Apparatus and method for implementing floating point additive and shift operations Nov. 29, 2011
8058899 Logic cell array and bus system Nov. 15, 2011
8051123 Multipurpose functional unit with double-precision and filtering operations Nov. 1, 2011
8046399 Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module Oct. 25, 2011
8041759 Specialized processing block for programmable logic device Oct. 18, 2011
8037118 Three-path fused multiply-adder circuit Oct. 11, 2011
8024393 Processor with improved accuracy for multiply-add operations Sep. 20, 2011
7991817 Method and a circuit using an associative calculator for calculating a sequence of non-associative operations Aug. 2, 2011
7966609 Optimal floating-point expression translation method based on pattern matching Jun. 21, 2011
7912887 Mode-based multiply-add recoding for denormal operands Mar. 22, 2011
7840622 Method and floating point unit to convert a hexadecimal floating point number to a binary floating point number Nov. 23, 2010
7728624 Circuit architecture for an integrated circuit Jun. 1, 2010
7720900 Fused multiply add split for multiple precision arithmetic May. 18, 2010
7716266 Common shift-amount calculation for binary and hex floating point May. 11, 2010
7659911 Method and apparatus for lossless and minimal-loss color conversion Feb. 9, 2010
7595659 Logic cell array and bus system Sep. 29, 2009
7543013 Multi-stage floating-point accumulator Jun. 2, 2009
7509366 Multiplier array processing system with enhanced utilization at lower precision Mar. 24, 2009
7499962 Enhanced fused multiply-add operation Mar. 3, 2009
7490119 High speed adder design for a multiply-add based floating point unit Feb. 10, 2009
7480690 Arithmetic circuit with multiplexed addend inputs Jan. 20, 2009

1 2 3 4










 
 
  Recently Added Patents
Method and system for parallelizing data copy in a distributed file system
Antimony and germanium complexes useful for CVD/ALD of metal thin films
Double patterning method using tilt-angle deposition
Epitaxial substrate for electronic device, in which current flows in lateral direction and method of producing the same
Traffic flow analysis mitigation using a cover signal
Zoom lens
Digital broadcast receiver and method for processing caption thereof
  Randomly Featured Patents
Handle magnet
Process for the preparation of polyisocyanates containing biuret and/or higher polyuret groups and use thereof as synthesis component in the preparation of polyurethane plastics
System and method for selectively printing color content of a page with a reduced color gamut and billing based on printed content
Multilayer stack with compensated resonant circuit
Controlling transmission of cell information between control nodes in radio access network
Canister with adjustable grinder
Apparatus for hanging a string of lights
Motorcycle master cylinder cover
Methods and compositions using terfenadine metabolites in combination with leukotriene inhibitors
Switchable support element