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Class Information
Number: 708/501
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Multiplication followed by addition
Description: Subject matter wherein the operation performed is multiplication followed by an addition.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7595659 |
Logic cell array and bus system |
Sep. 29, 2009 |
| 7543013 |
Multi-stage floating-point accumulator |
Jun. 2, 2009 |
| 7509366 |
Multiplier array processing system with enhanced utilization at lower precision |
Mar. 24, 2009 |
| 7499962 |
Enhanced fused multiply-add operation |
Mar. 3, 2009 |
| 7490119 |
High speed adder design for a multiply-add based floating point unit |
Feb. 10, 2009 |
| 7480690 |
Arithmetic circuit with multiplexed addend inputs |
Jan. 20, 2009 |
| 7461117 |
Floating point unit with fused multiply add and method for calculating a result with a floating point unit |
Dec. 2, 2008 |
| 7451172 |
Handling denormal floating point operands when result must be normalized |
Nov. 11, 2008 |
| 7444366 |
Faster shift value calculation using modified carry-lookahead adder |
Oct. 28, 2008 |
| 7428566 |
Multipurpose functional unit with multiply-add and format conversion pipeline |
Sep. 23, 2008 |
| 7392273 |
High-sticky calculation in pipelined fused multiply/add circuitry |
Jun. 24, 2008 |
| 7392274 |
Multi-function floating point arithmetic pipeline |
Jun. 24, 2008 |
| 7392270 |
Apparatus and method for reducing the latency of sum-addressed shifters |
Jun. 24, 2008 |
| 7346643 |
Processor with improved accuracy for multiply-add operations |
Mar. 18, 2008 |
| 7290023 |
High performance implementation of exponent adjustment in a floating point design |
Oct. 30, 2007 |
| 7254698 |
Multifunction hexadecimal instructions |
Aug. 7, 2007 |
| 7240085 |
Faster shift value calculation using modified carry-lookahead adder |
Jul. 3, 2007 |
| 7225216 |
Method and system for a floating point multiply-accumulator |
May. 29, 2007 |
| 7225323 |
Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines |
May. 29, 2007 |
| 7216139 |
Programmable logic device including multipliers and configurations thereof to reduce resource utilization |
May. 8, 2007 |
| 7194498 |
Higher radix multiplier with simplified partial product generator |
Mar. 20, 2007 |
| 7080111 |
Floating point multiply accumulator |
Jul. 18, 2006 |
| 7058830 |
Power saving in a floating point unit using a multiplier and aligner bypass |
Jun. 6, 2006 |
| 7027597 |
Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 7027598 |
Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits |
Apr. 11, 2006 |
| 6988184 |
Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations |
Jan. 17, 2006 |
| 6965908 |
Multi-function floating point arithmetic pipeline |
Nov. 15, 2005 |
| 6963894 |
Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation |
Nov. 8, 2005 |
| 6904446 |
Floating point multiplier/accumulator with reduced latency and method thereof |
Jun. 7, 2005 |
| 6895423 |
Apparatus and method of performing product-sum operation |
May. 17, 2005 |
| 6857061 |
Method and apparatus for obtaining a scalar value directly from a vector register |
Feb. 15, 2005 |
| 6842765 |
Processor design for extended-precision arithmetic |
Jan. 11, 2005 |
| 6820106 |
Method and apparatus for improving the performance of a floating point multiplier accumulator |
Nov. 16, 2004 |
| 6813626 |
Method and apparatus for performing fused instructions by determining exponent differences |
Nov. 2, 2004 |
| 6784888 |
Method and apparatus for executing a predefined instruction set |
Aug. 31, 2004 |
| 6779008 |
Method and apparatus for binary leading zero counting with constant-biased result |
Aug. 17, 2004 |
| 6757813 |
Processor |
Jun. 29, 2004 |
| 6751644 |
Method and apparatus for elimination of inherent carries |
Jun. 15, 2004 |
| 6701337 |
Floating-point calculator |
Mar. 2, 2004 |
| 6697832 |
Floating-point processor with improved intermediate result handling |
Feb. 24, 2004 |
| 6687810 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit |
Feb. 3, 2004 |
| 6643768 |
Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder |
Nov. 4, 2003 |
| 6631391 |
Parallel computer system and parallel computing method |
Oct. 7, 2003 |
| 6631461 |
Dyadic DSP instructions for digital signal processors |
Oct. 7, 2003 |
| 6615341 |
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control |
Sep. 2, 2003 |
| 6606700 |
DSP with dual-mac processor and dual-mac coprocessor |
Aug. 12, 2003 |
| 6584482 |
Multiplier array processing system with enhanced utilization at lower precision |
Jun. 24, 2003 |
| 6571266 |
Method for acquiring FMAC rounding parameters |
May. 27, 2003 |
| 6553120 |
Method for data decorrelation |
Apr. 22, 2003 |
| 6542916 |
Data processing apparatus and method for applying floating-point operations to first, second and third operands |
Apr. 1, 2003 |
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