| Patent Number |
Title Of Patent |
Date Issued |
| 7593977 |
Method and system for avoiding underflow in a floating-point operation |
Sep. 22, 2009 |
| 7373489 |
Apparatus and method for floating-point exception prediction and recovery |
May. 13, 2008 |
| 7272623 |
Methods and apparatus for determining a floating-point exponent associated with an underflow condition or an overflow condition |
Sep. 18, 2007 |
| 7120661 |
Bit exactness support in dual-MAC architecture |
Oct. 10, 2006 |
| 7103621 |
Processor efficient transformation and lighting implementation for three dimensional graphics utilizing scaled conversion instructions |
Sep. 5, 2006 |
| 7047270 |
Reporting a saturated counter value |
May. 16, 2006 |
| 6993545 |
Digital filter with protection against overflow oscillation |
Jan. 31, 2006 |
| 6993549 |
System and method for performing gloating point operations involving extended exponents |
Jan. 31, 2006 |
| 6963894 |
Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation |
Nov. 8, 2005 |
| 6947962 |
Overflow prediction algorithm and logic for high speed arithmetic units |
Sep. 20, 2005 |
| 6714957 |
System and method for efficient processing of denormal results as hardware exceptions |
Mar. 30, 2004 |
| 6687898 |
Optimization of n-base typed arithmetic expressions |
Feb. 3, 2004 |
| 6633895 |
Apparatus and method for sharing overflow/underflow compare hardware in a floating-point multiply-accumulate (FMAC) or floating-point adder (FADD) unit |
Oct. 14, 2003 |
| 6631392 |
Method and apparatus for predicting floating-point exceptions |
Oct. 7, 2003 |
| 6571265 |
Mechanism to detect IEEE underflow exceptions on speculative floating-point operations |
May. 27, 2003 |
| 6535900 |
Accumulation saturation by means of feedback |
Mar. 18, 2003 |
| 6529930 |
Methods and apparatus for performing a signed saturation operation |
Mar. 4, 2003 |
| 6490607 |
Shared FP and SIMD 3D multiplier |
Dec. 3, 2002 |
| 6484251 |
Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor |
Nov. 19, 2002 |
| 6411978 |
Mechanism for block floating point FFT hardware support on a fixed point digital signal processor |
Jun. 25, 2002 |
| 6408379 |
Apparatus and method for executing floating-point store instructions in a microprocessor |
Jun. 18, 2002 |
| 6243731 |
Apparatus and method for extending register dynamic range |
Jun. 5, 2001 |
| 6219684 |
Optimized rounding in underflow handlers |
Apr. 17, 2001 |
| 6219685 |
Method to detect IEEE overflow and underflow conditions |
Apr. 17, 2001 |
| 6199089 |
Floating point arithmetic logic unit rounding using at least one least significant bit |
Mar. 6, 2001 |
| 6151669 |
Methods and apparatus for efficient control of floating-point status register |
Nov. 21, 2000 |
| 6122651 |
Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions |
Sep. 19, 2000 |
| 6037947 |
Graphics accelerator with shift count generation for handling potential fixed-point numeric overflows |
Mar. 14, 2000 |
| 5996056 |
Apparatus for reducing a computational result to the range boundaries of a signed 8-bit integer in case of overflow |
Nov. 30, 1999 |
| 5905663 |
Minimal circuit for detecting loss of precision in floating point numbers |
May. 18, 1999 |
| 5903479 |
Method and system for executing denormalized numbers |
May. 11, 1999 |
| 5689721 |
Detecting overflow conditions for negative quotients in nonrestoring two's complement division |
Nov. 18, 1997 |
| 5602769 |
Method and apparatus for partially supporting subnormal operands in floating point multiplication |
Feb. 11, 1997 |
| 5553015 |
Efficient floating point overflow and underflow detection system |
Sep. 3, 1996 |
| 5550767 |
Method and apparatus for detecting underflow and overflow |
Aug. 27, 1996 |
| 5481489 |
Method of and apparatus for discriminating NaN |
Jan. 2, 1996 |
| 5341320 |
Method for rapidly processing floating-point operations which involve exceptions |
Aug. 23, 1994 |
| 5317527 |
Leading one/zero bit detector for floating point operation |
May. 31, 1994 |
| 5289396 |
Floating point processor with high speed rounding circuit |
Feb. 22, 1994 |
| 5257216 |
Floating point safe instruction recognition apparatus |
Oct. 26, 1993 |
| 5257214 |
Qualification of register file write enables using self-timed floating point exception flags |
Oct. 26, 1993 |
| 5257215 |
Floating point and integer number conversions in a floating point adder |
Oct. 26, 1993 |
| 5235533 |
Store rounding in a floating point unit |
Aug. 10, 1993 |
| 5038313 |
Floating-point processor provided with high-speed detector of overflow and underflow exceptional conditions |
Aug. 6, 1991 |
| 4839846 |
Apparatus for performing floating point arithmetic operations and rounding the result thereof |
Jun. 13, 1989 |
| 4779220 |
Floating-point data rounding and normalizing circuit |
Oct. 18, 1988 |
| 4683546 |
Floating point condition code generation |
Jul. 28, 1987 |
| 4590584 |
Method and system for processing exponents in floating-point multiplication |
May. 20, 1986 |
| 4534010 |
Floating point type multiplier circuit with compensation for over-flow and under-flow in multiplication of numbers in two's compliment representation |
Aug. 6, 1985 |
