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Class Information
Number: 708/496
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Arithmetical operation > Floating point > Compensation for finite word length
Description: Subject matter wherein the operation results in a word modification in length due to insufficient representation of using the fixed word length of the arithmetic system.


Sub-classes under this class:

Class Number Class Name Patents
708/498 Overflow or underflow 49
708/497 Round off or truncation 113
708/499 Sticky bit 36


Patents under this class:

Patent Number Title Of Patent Date Issued
RE40883 Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision Aug. 25, 2009
7447725 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units Nov. 4, 2008
7222146 Method and apparatus for facilitating exception-free arithmetic in a computer system May. 22, 2007
7099851 Applying term consistency to an equality constrained interval global optimization problem Aug. 29, 2006
7058830 Power saving in a floating point unit using a multiplier and aligner bypass Jun. 6, 2006
6981012 Method and circuit for normalization of floating point significants in a SIMD array MPP Dec. 27, 2005
6728739 Data calculating device and method for processing data in data block form Apr. 27, 2004
6578059 Methods and apparatus for controlling exponent range in floating-point calculations Jun. 10, 2003
6557021 Rounding anticipator for floating point operations Apr. 29, 2003
6430677 Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision Aug. 6, 2002
6219684 Optimized rounding in underflow handlers Apr. 17, 2001
6138135 Propagating NaNs during high precision calculations using lesser precision hardware Oct. 24, 2000
6049865 Method and apparatus for implementing floating point projection instructions Apr. 11, 2000
5966085 Methods and apparatus for performing fast floating point operations Oct. 12, 1999
5943249 Method and apparatus to perform pipelined denormalization of floating-point results Aug. 24, 1999
5894428 Recursive digital filter Apr. 13, 1999
5892697 Method and apparatus for handling overflow and underflow in processing floating-point numbers Apr. 6, 1999
5809292 Floating point for simid array machine Sep. 15, 1998
5805487 Method and system for fast determination of sticky and guard bits Sep. 8, 1998
5781464 Apparatus and method for incrementing floating-point numbers represented in diffrent precision modes Jul. 14, 1998
5619711 Method and data processing system for arbitrary precision on numbers Apr. 8, 1997
5408427 Detection of exponent underflow and overflow in a floating point adder Apr. 18, 1995
5309383 Floating-point division circuit May. 3, 1994
5212662 Floating point arithmetic two cycle data flow May. 18, 1993
5197023 Hardware arrangement for floating-point addition and subtraction Mar. 23, 1993
RE33629 Numeric data processor Jul. 2, 1991
5027308 Circuit for adding/subtracting two floating point operands Jun. 25, 1991
4999802 Floating point arithmetic two cycle data flow Mar. 12, 1991
4994996 Pipelined floating point adder for digital computer Feb. 19, 1991
4943940 Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus Jul. 24, 1990
4800516 High speed floating-point unit Jan. 24, 1989
4788655 Condition code producing system Nov. 29, 1988
4773035 Pipelined data processing system utilizing ideal floating point execution condition detection Sep. 20, 1988
4649508 Floating-point arithmetic operation system Mar. 10, 1987
4366548 Adder for exponent arithmetic Dec. 28, 1982
4338675 Numeric data processor Jul. 6, 1982
4282582 Floating point processor architecture which performs subtraction with reduced number of guard bits Aug. 4, 1981



 
 
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