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Class Information
Number: 708/205
Name: Electrical computers: arithmetic processing and calculating > Electrical digital calculating computer > Particular function performed > Format conversion > Normalization
Description: Subject matter in which the number in final form includes a single nonzero digit to the left of a radix point.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7590673 |
Normalization at constant flow of a noise source for random number generation |
Sep. 15, 2009 |
| 7430656 |
System and method of converting data formats and communicating between execution units |
Sep. 30, 2008 |
| 7248700 |
Device and method for calculating a result of a modular exponentiation |
Jul. 24, 2007 |
| 7096241 |
Exponent encoder circuit and mask circuit |
Aug. 22, 2006 |
| 7086004 |
Generalized mechanism for unicode metadata |
Aug. 1, 2006 |
| 7062657 |
Methods and apparatus for hardware normalization and denormalization |
Jun. 13, 2006 |
| 6988115 |
Method and apparatus to correct leading one prediction |
Jan. 17, 2006 |
| 6981012 |
Method and circuit for normalization of floating point significants in a SIMD array MPP |
Dec. 27, 2005 |
| 6922159 |
Apparatus and method for decoding |
Jul. 26, 2005 |
| 6901503 |
Data processing circuits and interfaces |
May. 31, 2005 |
| 6779008 |
Method and apparatus for binary leading zero counting with constant-biased result |
Aug. 17, 2004 |
| 6765515 |
Arithmetic coding/decoding apparatus of MQ-Coder system and renormalization method |
Jul. 20, 2004 |
| 6760738 |
Exponent unit of data processing system |
Jul. 6, 2004 |
| 6754688 |
Method and apparatus to calculate the difference of two numbers |
Jun. 22, 2004 |
| 6675376 |
System and method for fusing instructions |
Jan. 6, 2004 |
| 6671796 |
Converting an arbitrary fixed point value to a floating point value |
Dec. 30, 2003 |
| 6622118 |
System and method for comparing signals |
Sep. 16, 2003 |
| 6571264 |
Floating-point arithmetic device |
May. 27, 2003 |
| 6499044 |
Leading zero/one anticipator for floating point |
Dec. 24, 2002 |
| 6360238 |
Leading zero/one anticipator having an integrated sign selector |
Mar. 19, 2002 |
| 6301594 |
Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers |
Oct. 9, 2001 |
| 6289366 |
Speedy shift apparatus for use in arithmetic unit |
Sep. 11, 2001 |
| 6219682 |
Vector normalizing apparatus |
Apr. 17, 2001 |
| 6185593 |
Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations |
Feb. 6, 2001 |
| 6178437 |
Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor |
Jan. 23, 2001 |
| 6175847 |
Shifting for parallel normalization and rounding technique for floating point arithmetic operations |
Jan. 16, 2001 |
| 6173300 |
Method and circuit for determining leading or trailing zero count |
Jan. 9, 2001 |
| 6173299 |
Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations |
Jan. 9, 2001 |
| 6154760 |
Instruction to normalize redundantly encoded floating point numbers |
Nov. 28, 2000 |
| 6108678 |
Method and apparatus to detect a floating point mantissa of all zeros or all ones |
Aug. 22, 2000 |
| 6101516 |
Normalization shift prediction independent of operand subtraction |
Aug. 8, 2000 |
| 6085211 |
Logic circuit and floating-point arithmetic unit |
Jul. 4, 2000 |
| 6085208 |
Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit |
Jul. 4, 2000 |
| 6061749 |
Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword |
May. 9, 2000 |
| 6018756 |
Reduced-latency floating-point pipeline using normalization shifts of both operands |
Jan. 25, 2000 |
| 5974432 |
On-the-fly one-hot encoding of leading zero count |
Oct. 26, 1999 |
| 5963461 |
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization |
Oct. 5, 1999 |
| 5957997 |
Efficient floating point normalization mechanism |
Sep. 28, 1999 |
| 5948049 |
Normalization circuitry |
Sep. 7, 1999 |
| 5931895 |
Floating-point arithmetic processing apparatus |
Aug. 3, 1999 |
| 5923574 |
Optimized, combined leading zeros counter and shifter |
Jul. 13, 1999 |
| 5923575 |
Method for eletronically representing a number, adder circuit and computer system |
Jul. 13, 1999 |
| 5920493 |
Apparatus and method to determine a most significant bit |
Jul. 6, 1999 |
| 5903479 |
Method and system for executing denormalized numbers |
May. 11, 1999 |
| 5867407 |
Normalization shift prediction independent of operand substraction |
Feb. 2, 1999 |
| 5844827 |
Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N |
Dec. 1, 1998 |
| 5841683 |
Least significant bit and guard bit extractor |
Nov. 24, 1998 |
| 5808923 |
Denormalization device and method for multichannel audio decoder |
Sep. 15, 1998 |
| 5798953 |
Apparatus and method for determining a number of digits leading a particular digit |
Aug. 25, 1998 |
| 5796644 |
Floating-point multiply-and-accumulate unit with classes for alignment and normalization |
Aug. 18, 1998 |
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