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Class Information
Number: 703/19
Name: Data processing: structural design, modeling, simulation, and emulation > Simulating electronic device or electrical system > Timing
Description: Subject matter wherein the timing delay of the electrical device or the electrical system is being simulated.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6553338 Timing optimization in presence of interconnect delays Apr. 22, 2003
6507936 Timing verifying method Jan. 14, 2003
6505149 Method and system for verifying a source-synchronous communication interface of a device Jan. 7, 2003
6493660 Delay time calculating method for use in hierarchical design Dec. 10, 2002
6466898 Multithreaded, mixed hardware description languages logic simulation on engineering workstations Oct. 15, 2002
6418401 Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation Jul. 9, 2002
6397169 Adaptive cell separation and circuit changes driven by maximum capacitance rules May. 28, 2002
6397341 Method for improving the speed of behavioral synthesis links to logic synthesis May. 28, 2002
6393480 Application response time prediction May. 21, 2002
6389381 Method and apparatus for calculating delay times in semiconductor circuit May. 14, 2002
6378113 Black box transparency in a circuit timing model Apr. 23, 2002
6370495 Method and apparatus for simulating a storage component Apr. 9, 2002
6356862 Hardware and software co-verification employing deferred synchronization Mar. 12, 2002
6353917 Determining a worst case switching factor for integrated circuit design Mar. 5, 2002
6338025 Data processing system and method to estimate power in mixed dynamic/static CMOS designs Jan. 8, 2002
6327552 Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves Dec. 4, 2001
6321366 Timing-insensitive glitch-free logic system and method Nov. 20, 2001
6311147 Integrated circuit power net analysis Oct. 30, 2001
6311148 Method for determining static flip-flop setup and hold times Oct. 30, 2001
6301553 Method and apparatus for removing timing hazards in a circuit design Oct. 9, 2001
6298320 System and method for testing an embedded microprocessor system containing physical and/or simulated hardware Oct. 2, 2001
6295632 System and method for detecting the output of a clock driver Sep. 25, 2001
6278964 Hot carrier effect simulation for integrated circuits Aug. 21, 2001
6275784 Design method of routing signal lines between circuit blocks for equalizing characteristics of circuit blocks and semiconductor integrated circuit device designed therethrough Aug. 14, 2001
6263303 Simulator architecture Jul. 17, 2001
6263301 Method and apparatus for storing and viewing data generated from a computer simulation of an integrated circuit Jul. 17, 2001
6263302 Hardware and software co-simulation including simulating the cache of a target processor Jul. 17, 2001
6237127 Static timing analysis of digital electronic circuits using non-default constraints known as exceptions May. 22, 2001
6230115 Simulator, simulation method, and medium having simulation program recorded, taking account of timing in electronic component and signal transmission through transmission line on printed-circu May. 8, 2001
6230302 Method and system for performing timing analysis on an integrated circuit design May. 8, 2001
6230294 Transient analysis device for analog/digital mixed circuit and analysis method thereof May. 8, 2001
6223141 Speeding up levelized compiled code simulation using netlist transformations Apr. 24, 2001
6216255 Computer-aided logic circuit designing apparatus computer-aided logic circuit designing system, and computer-aided logic circuit designing method Apr. 10, 2001
6212490 Hybrid circuit model simulator for accurate timing and noise analysis Apr. 3, 2001
6195623 Time-frequency method and apparatus for simulating the initial transient response of quartz oscillators Feb. 27, 2001
6185723 Method for performing timing analysis of a clock-shaping circuit Feb. 6, 2001
6185518 Method and system for logic design constraint generation Feb. 6, 2001
6173432 Method and apparatus for generating a sequence of clock signals Jan. 9, 2001
6169968 Apparatus and method for estimating performance integrated circuit Jan. 2, 2001
6167364 Methods and apparatus for automatically generating interconnect patterns in programmable logic devices Dec. 26, 2000
6161081 Simulation model for a digital system Dec. 12, 2000
6138267 Reliability verification device for detecting portion of design that may cause malfunction of semiconductor integrated circuit and its verifying method Oct. 24, 2000
6131181 Method and system for identifying tested path delay faults Oct. 10, 2000
6128769 Method for analyzing and efficiently reducing signal cross-talk noise Oct. 3, 2000
6110219 Model for taking into account gate resistance induced propagation delay Aug. 29, 2000
6093212 Method for selecting operation cycles of a semiconductor IC for performing an IDDQ test by using a simulation Jul. 25, 2000
6090150 Method of designing clock wiring and apparatus for implementing the same Jul. 18, 2000
6090152 Method and system for using voltage and temperature adders to account for variations in operating conditions during timing simulation Jul. 18, 2000
6086621 Logic synthesis constraints allocation automating the concurrent engineering flows Jul. 11, 2000
6085307 Multiple native instruction set master/slave processor arrangement and method thereof Jul. 4, 2000

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