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Class Information
Number: 703/19
Name: Data processing: structural design, modeling, simulation, and emulation > Simulating electronic device or electrical system > Timing
Description: Subject matter wherein the timing delay of the electrical device or the electrical system is being simulated.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7600206 |
Method of estimating the signal delay in a VLSI circuit |
Oct. 6, 2009 |
| 7596483 |
Determining timing of integrated circuits |
Sep. 29, 2009 |
| 7596775 |
Method for determining a standard cell for IC design |
Sep. 29, 2009 |
| 7587691 |
Method and apparatus for facilitating variation-aware parasitic extraction |
Sep. 8, 2009 |
| 7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level |
Aug. 25, 2009 |
| 7580037 |
Techniques for graphical analysis and manipulation of circuit timing requirements |
Aug. 25, 2009 |
| 7571398 |
Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits |
Aug. 4, 2009 |
| 7571412 |
Method and system for semiconductor device characterization pattern generation and analysis |
Aug. 4, 2009 |
| 7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths |
Jun. 30, 2009 |
| 7555419 |
Simulation of system execution of instructions |
Jun. 30, 2009 |
| 7555417 |
Selectively reducing the number of cell evaluations in a hardware simulation |
Jun. 30, 2009 |
| 7552040 |
Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects |
Jun. 23, 2009 |
| 7546559 |
Method of optimization of clock gating in integrated circuit designs |
Jun. 9, 2009 |
| 7542892 |
Reporting delay in modeling environments |
Jun. 2, 2009 |
| 7526745 |
Method for specification and integration of reusable IP constraints |
Apr. 28, 2009 |
| 7516383 |
Method and apparatus for analyzing delay in circuit, and computer product |
Apr. 7, 2009 |
| 7512918 |
Multimode delay analysis for simplifying integrated circuit design timing models |
Mar. 31, 2009 |
| 7506293 |
Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis |
Mar. 17, 2009 |
| 7500205 |
Skew reduction for generated clocks |
Mar. 3, 2009 |
| 7496491 |
Delay calculation method capable of calculating delay time with small margin of error |
Feb. 24, 2009 |
| 7487078 |
Method and system for modeling distributed time invariant systems |
Feb. 3, 2009 |
| 7487475 |
Systems, methods, and apparatus to perform statistical static timing analysis |
Feb. 3, 2009 |
| 7487482 |
Method and system for evaluating a constraint of a sequential cell |
Feb. 3, 2009 |
| 7484196 |
Method for asynchronous clock modeling in an integrated circuit simulation |
Jan. 27, 2009 |
| 7483823 |
Building integrated circuits using logical units |
Jan. 27, 2009 |
| 7480607 |
Circuit design verification |
Jan. 20, 2009 |
| 7478027 |
Systems, methods, and media for simulation of integrated hardware and software designs |
Jan. 13, 2009 |
| 7478030 |
Clock stabilization detection for hardware simulation |
Jan. 13, 2009 |
| 7478346 |
Debugging system for gate level IC designs |
Jan. 13, 2009 |
| 7467366 |
Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components |
Dec. 16, 2008 |
| 7460984 |
Compensating for delay in modeling environments |
Dec. 2, 2008 |
| 7444607 |
Method for correcting timing error when designing semiconductor integrated circuit |
Oct. 28, 2008 |
| 7444574 |
Stimulus extraction and sequence generation for an electric device under test |
Oct. 28, 2008 |
| 7437696 |
Method and device for determining the time response of a digital circuit |
Oct. 14, 2008 |
| 7437695 |
Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices |
Oct. 14, 2008 |
| 7424417 |
System and method for clock domain grouping using data path relationships |
Sep. 9, 2008 |
| 7421675 |
Annotating timing information for a circuit design for increased timing accuracy |
Sep. 2, 2008 |
| 7415404 |
Method and apparatus for generating a sequence of clock signals |
Aug. 19, 2008 |
| 7409329 |
Flexible SPDIF verification tool |
Aug. 5, 2008 |
| 7403885 |
Voltage supply noise analysis |
Jul. 22, 2008 |
| 7403884 |
Transient simulation using adaptive piecewise constant model |
Jul. 22, 2008 |
| 7398445 |
Method and system for debug and test using replicated logic |
Jul. 8, 2008 |
| 7395519 |
Electronic-circuit analysis program, method, and apparatus for waveform analysis |
Jul. 1, 2008 |
| 7380228 |
Method of associating timing violations with critical structures in an integrated circuit design |
May. 27, 2008 |
| 7379855 |
Method and apparatus for timing modeling |
May. 27, 2008 |
| 7380226 |
Systems, methods, and apparatus to perform logic synthesis preserving high-level specification |
May. 27, 2008 |
| 7370302 |
Partitioning a large design across multiple devices |
May. 6, 2008 |
| 7366648 |
Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program |
Apr. 29, 2008 |
| 7363610 |
Building integrated circuits using a common database |
Apr. 22, 2008 |
| 7359843 |
Robust calculation of crosstalk delay change in integrated circuit design |
Apr. 15, 2008 |
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