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Class Information
Number: 703/15
Name: Data processing: structural design, modeling, simulation, and emulation > Simulating electronic device or electrical system > Circuit simulation > Including logic
Description: Subject matter wherein the simulated circuit consists of logic circuit.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613599 |
Method and system for virtual prototyping |
Nov. 3, 2009 |
| 7606698 |
Method and apparatus for sharing data between discrete clusters of processors |
Oct. 20, 2009 |
| 7600169 |
Systems and methods of test case generation with feedback |
Oct. 6, 2009 |
| 7596483 |
Determining timing of integrated circuits |
Sep. 29, 2009 |
| 7587305 |
Transistor level verilog |
Sep. 8, 2009 |
| 7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level |
Aug. 25, 2009 |
| 7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium |
Aug. 11, 2009 |
| 7571087 |
Computer storage exception handling apparatus and method for virtual hardware system |
Aug. 4, 2009 |
| 7571086 |
Incremental circuit re-simulation system |
Aug. 4, 2009 |
| 7567137 |
Programmable oscillators for high frequency clock generation for simulation environments |
Jul. 28, 2009 |
| 7558722 |
Debug method for mismatches occurring during the simulation of scan patterns |
Jul. 7, 2009 |
| 7555416 |
Efficient transistor-level circuit simulation |
Jun. 30, 2009 |
| 7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths |
Jun. 30, 2009 |
| 7552043 |
Method, system and program product for selectively removing instrumentation logic from a simulation model |
Jun. 23, 2009 |
| 7546561 |
System and method of state point correspondence with constrained function determination |
Jun. 9, 2009 |
| 7536289 |
Method of configuring information processing system and semiconductor integrated circuit |
May. 19, 2009 |
| 7533011 |
Simulating and verifying signal glitching |
May. 12, 2009 |
| 7519524 |
Program product for providing a configuration specification language supporting incompletely specified configuration entities |
Apr. 14, 2009 |
| 7519525 |
Post initial microcode load co-simulation method, system, and program product |
Apr. 14, 2009 |
| 7516383 |
Method and apparatus for analyzing delay in circuit, and computer product |
Apr. 7, 2009 |
| 7512918 |
Multimode delay analysis for simplifying integrated circuit design timing models |
Mar. 31, 2009 |
| 7512912 |
Method and apparatus for solving constraints for word-level networks |
Mar. 31, 2009 |
| 7512531 |
Method and apparatus for specifying reactive systems |
Mar. 31, 2009 |
| 7509599 |
Method and apparatus for performing formal verification using data-flow graphs |
Mar. 24, 2009 |
| 7505887 |
Building a simulation of design block using a bus functional model and an HDL testbench |
Mar. 17, 2009 |
| 7506286 |
Method and system for debugging an electronic system |
Mar. 17, 2009 |
| 7506284 |
Event driven switch level simulation method and simulator |
Mar. 17, 2009 |
| 7502728 |
Code coverage testing in hardware emulation |
Mar. 10, 2009 |
| 7496820 |
Method and apparatus for generating test vectors for an integrated circuit under test |
Feb. 24, 2009 |
| 7493578 |
Correlation of data from design analysis tools with design blocks in a high-level modeling system |
Feb. 17, 2009 |
| 7493544 |
Extending test sequences to accepting states |
Feb. 17, 2009 |
| 7487076 |
Simplified data signal support for diagramming environment languages |
Feb. 3, 2009 |
| 7483824 |
Self-checking test generator for partially-modeled processors by propagating fuzzy states |
Jan. 27, 2009 |
| 7484156 |
Apparatus and method for testing PS/2 interface |
Jan. 27, 2009 |
| 7480879 |
Substrate noise tool |
Jan. 20, 2009 |
| 7480608 |
Method and system for reducing storage requirements of simulation data via KEYWORD restrictions |
Jan. 20, 2009 |
| 7480604 |
Method of modeling and producing an integrated circuit including at least one transistor and corresponding integrated circuit |
Jan. 20, 2009 |
| 7480602 |
System verification test using a behavior model |
Jan. 20, 2009 |
| 7478028 |
Method for automatically searching for functional defects in a description of a circuit |
Jan. 13, 2009 |
| 7478029 |
Cable simulation device and method |
Jan. 13, 2009 |
| 7478304 |
Apparatus for accelerating through-the-pins LBIST simulation |
Jan. 13, 2009 |
| 7478346 |
Debugging system for gate level IC designs |
Jan. 13, 2009 |
| 7464015 |
Method and apparatus for supporting verification, and computer product |
Dec. 9, 2008 |
| 7464287 |
Strategy to verify asynchronous links across chips |
Dec. 9, 2008 |
| 7460988 |
Test emulator, test module emulator, and record medium storing program therein |
Dec. 2, 2008 |
| 7454323 |
Method for creation of secure simulation models |
Nov. 18, 2008 |
| 7454325 |
Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases |
Nov. 18, 2008 |
| 7451426 |
Application specific configurable logic IP |
Nov. 11, 2008 |
| 7447620 |
Modeling asynchronous behavior from primary inputs and latches |
Nov. 4, 2008 |
| 7447966 |
Hardware verification scripting |
Nov. 4, 2008 |
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