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Class Information
Number: 438/969
Name: Semiconductor device manufacturing: process > Simultaneous formation of monocrystalline and polycrystalline regions
Description: Art collection involving the simultaneous formation of single crystalline and polycrystalline regions.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8293626 Method for manufacturing semiconductor device Oct. 23, 2012
8236603 Polycrystalline semiconductor layers and methods for forming the same Aug. 7, 2012
7994017 Method of manufacturing silicon carbide self-aligned epitaxial MOSFET for high powered device applications Aug. 9, 2011
7972919 Vertical PNP transistor and method of making same Jul. 5, 2011
7572715 Selective epitaxy process with alternating gas supply Aug. 11, 2009
7560352 Selective deposition Jul. 14, 2009
7557010 Method to improve writer leakage in a SiGe bipolar device Jul. 7, 2009
7312128 Selective epitaxy process with alternating gas supply Dec. 25, 2007
7265010 High performance vertical PNP transistor method Sep. 4, 2007
7227186 Thin film transistor and method of manufacturing the same Jun. 5, 2007
7067341 Single electron transistor manufacturing method by electro-migration of metallic nanoclusters Jun. 27, 2006
6991999 Bi-layer silicon film and method of fabrication Jan. 31, 2006
6964892 N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same Nov. 15, 2005
6909164 High performance vertical PNP transistor and method Jun. 21, 2005
6884699 Process and unit for production of polycrystalline silicon film Apr. 26, 2005
6593174 Field effect transistor having dielectrically isolated sources and drains and method for making same Jul. 15, 2003
6500717 Method for making an integrated circuit device with dielectrically isolated tubs and related circuit Dec. 31, 2002
6407014 Method achieving higher inversion layer mobility in novel silicon carbide semiconductor devices Jun. 18, 2002
6337255 Method for forming a trench structure in a silicon substrate Jan. 8, 2002
6184059 Process of making diamond-metal ohmic junction semiconductor device Feb. 6, 2001
6171935 Process for producing an epitaxial layer with laterally varying doping Jan. 9, 2001
5998844 Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon Dec. 7, 1999
5913135 Method for forming planar field effect transistors with source and drain on oxide and device constructed therefrom Jun. 15, 1999
5840613 Fabrication method for semiconductor device Nov. 24, 1998
5831334 Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon Nov. 3, 1998
5693979 Semiconductor device Dec. 2, 1997
5648280 Method for fabricating a bipolar transistor with a base layer having an extremely low resistance Jul. 15, 1997
5637518 Method of making a field effect transistor having an elevated source and an elevated drain Jun. 10, 1997
5599723 Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance Feb. 4, 1997
5569611 Method of manufacturing a bipolar transistor operating at low temperature Oct. 29, 1996
5504018 Process of fabricating bipolar transistor having epitaxially grown base layer without deterioration of transistor characteristics Apr. 2, 1996
5494836 Process of producing heterojunction bipolar transistor with silicon-germanium base Feb. 27, 1996
5478774 Method of fabricating patterned-mirror VCSELs using selective growth Dec. 26, 1995
5476809 Semiconductor device and method of manufacturing the same Dec. 19, 1995
5432104 Method for fabricating a vertical bipolar transistor with reduced parasitic capacitance between base and collector regions Jul. 11, 1995
5296388 Fabrication method for semiconductor devices Mar. 22, 1994
5234845 Method of manufacturing semiconductor IC using selective poly and EPI silicon growth Aug. 10, 1993
5219767 Process for preparing semiconductor device Jun. 15, 1993
5114875 Planar dielectric isolated wafer May. 19, 1992
5110757 Formation of composite monosilicon/polysilicon layer using reduced-temperature two-step silicon deposition May. 5, 1992
5104823 Monolithic integration of optoelectronic and electronic devices Apr. 14, 1992
5096844 Method for manufacturing bipolar transistor by selective epitaxial growth of base and emitter layers Mar. 17, 1992
5084407 Method for planarizing isolated regions Jan. 28, 1992
5008207 Method of fabricating a narrow base transistor Apr. 16, 1991
4963505 Semiconductor device and method of manufacturing same Oct. 16, 1990
4949146 Structured semiconductor body Aug. 14, 1990
4925810 Compound semiconductor device and a method of manufacturing the same May. 15, 1990
4879255 Method for fabricating bipolar-MOS devices Nov. 7, 1989
4861426 Method of making a millimeter wave monolithic integrated circuit Aug. 29, 1989
4711858 Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer Dec. 8, 1987

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