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Class Information
Number: 438/926
Name: Semiconductor device manufacturing: process > Dummy metallization
Description: Art collection involving the use of an electrically conductive layer during semiconductor manufacture which is not utilized for the carrying of electrical current.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7585716 |
High-k/metal gate MOSFET with reduced parasitic capacitance |
Sep. 8, 2009 |
| 7531437 |
Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material |
May. 12, 2009 |
| 7528025 |
Nonplanar transistors with metal gate electrodes |
May. 5, 2009 |
| 7528033 |
Semiconductor device with a dummy gate and a method of manufacturing a semiconductor device with a dummy gate |
May. 5, 2009 |
| 7524747 |
Floating gate memory device and method of manufacturing the same |
Apr. 28, 2009 |
| 7521803 |
Semiconductor device having first and second dummy wirings varying in sizes/coverage ratios around a plug connecting part |
Apr. 21, 2009 |
| 7488634 |
Method for fabricating flash memory device |
Feb. 10, 2009 |
| 7482661 |
Pattern forming method and semiconductor device manufactured by using said pattern forming method |
Jan. 27, 2009 |
| 7465488 |
Bow control in an electronic package |
Dec. 16, 2008 |
| 7452804 |
Single damascene with disposable stencil and method therefore |
Nov. 18, 2008 |
| 7445966 |
Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof |
Nov. 4, 2008 |
| 7446039 |
Integrated circuit system with dummy region |
Nov. 4, 2008 |
| 7399675 |
Electronic device including an array and process for forming the same |
Jul. 15, 2008 |
| 7361574 |
Single-crystal silicon-on-glass from film transfer |
Apr. 22, 2008 |
| 7332439 |
Metal gate transistors with epitaxial source and drain regions |
Feb. 19, 2008 |
| 7314811 |
Method to make corner cross-grid structures in copper metallization |
Jan. 1, 2008 |
| 7298015 |
Three-dimensional structure element and method of manufacturing the element, optical switch, and micro device |
Nov. 20, 2007 |
| 7271045 |
Etch stop and hard mask film property matching to enable improved replacement metal gate process |
Sep. 18, 2007 |
| 7247530 |
Ultrathin SOI transistor and method of making the same |
Jul. 24, 2007 |
| 7226839 |
Method and system for improving the topography of a memory array |
Jun. 5, 2007 |
| 7217644 |
Method of manufacturing MOS devices with reduced fringing capacitance |
May. 15, 2007 |
| 7217611 |
Methods for integrating replacement metal gate structures |
May. 15, 2007 |
| 7214994 |
Self aligned metal gates on high-k dielectrics |
May. 8, 2007 |
| 7211492 |
Self aligned metal gates on high-k dielectrics |
May. 1, 2007 |
| 7186639 |
Metal interconnection lines of semiconductor devices and methods of forming the same |
Mar. 6, 2007 |
| 7176090 |
Method for making a semiconductor device that includes a metal gate electrode |
Feb. 13, 2007 |
| 7163853 |
Method of manufacturing a capacitor and a metal gate on a semiconductor device |
Jan. 16, 2007 |
| 7160794 |
Method of fabricating non-volatile memory |
Jan. 9, 2007 |
| 7157289 |
Method for homogenizing the thickness of a coating on a patterned layer |
Jan. 2, 2007 |
| 7074710 |
Method of wafer patterning for reducing edge exclusion zone |
Jul. 11, 2006 |
| 7071063 |
Dual-bit non-volatile memory cell and method of making the same |
Jul. 4, 2006 |
| 6972225 |
integrating n-type and P-type metal gate transistors |
Dec. 6, 2005 |
| 6955987 |
Comparison of chemical-mechanical polishing processes |
Oct. 18, 2005 |
| 6953719 |
Integrating n-type and p-type metal gate transistors |
Oct. 11, 2005 |
| 6951806 |
Metal region for reduction of capacitive coupling between signal lines |
Oct. 4, 2005 |
| 6943129 |
Interconnection structure and method for designing the same |
Sep. 13, 2005 |
| 6939726 |
Via array monitor and method of monitoring induced electrical charging |
Sep. 6, 2005 |
| 6930382 |
Semiconductor device and method of manufacturing the same |
Aug. 16, 2005 |
| 6916705 |
Semiconductor memory and method for fabricating the same |
Jul. 12, 2005 |
| 6884670 |
Dry etching with reduced damage to MOS device |
Apr. 26, 2005 |
| 6867080 |
Polysilicon tilting to prevent geometry effects during laser thermal annealing |
Mar. 15, 2005 |
| 6858483 |
Integrating n-type and p-type metal gate transistors |
Feb. 22, 2005 |
| 6849549 |
Method for forming dummy structures for improved CMP and reduced capacitance |
Feb. 1, 2005 |
| 6833622 |
Semiconductor topography having an inactive region formed from a dummy structure pattern |
Dec. 21, 2004 |
| 6791191 |
Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
Sep. 14, 2004 |
| 6782512 |
Fabrication method for a semiconductor device with dummy patterns |
Aug. 24, 2004 |
| 6780715 |
Method for fabricating merged dram with logic semiconductor device |
Aug. 24, 2004 |
| 6743644 |
Method of making a metallization line layout |
Jun. 1, 2004 |
| 6737351 |
Versatile system for diffusion limiting void formation |
May. 18, 2004 |
| 6717267 |
Semiconductor device having multilayer interconnection structure |
Apr. 6, 2004 |
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