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Class Information
Number: 438/744
Name: Semiconductor device manufacturing: process > Chemical etching > Vapor phase etching (i.e., dry etching) > Differential etching of semiconductor substrate > Substrate possessing multiple layers > Silicon nitride
Description: Process wherein the material undergoing etching with the energized gas is a compound of silicon and nitrogen.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7402513 |
Method for forming interlayer insulation film |
Jul. 22, 2008 |
| 7393791 |
Etching method, method of fabricating metal film structure, and etching structure |
Jul. 1, 2008 |
| 7358595 |
Method for manufacturing MOS transistor |
Apr. 15, 2008 |
| 7354867 |
Etch process for improving yield of dielectric contacts on nickel silicides |
Apr. 8, 2008 |
| 7326358 |
Plasma processing method and apparatus, and storage medium |
Feb. 5, 2008 |
| 7316785 |
Methods and apparatus for the optimization of etch resistance in a plasma processing system |
Jan. 8, 2008 |
| 7309656 |
Method for forming step channel of semiconductor device |
Dec. 18, 2007 |
| RE39895 |
Semiconductor integrated circuit arrangement fabrication method |
Oct. 23, 2007 |
| 7276450 |
Etching processes using C.sub.4F.sub.8 for silicon dioxide and CF.sub.4 for titanium nitride |
Oct. 2, 2007 |
| 7265026 |
Method of forming a shallow trench isolation structure in a semiconductor device |
Sep. 4, 2007 |
| 7256134 |
Selective etching of carbon-doped low-k dielectrics |
Aug. 14, 2007 |
| 7244644 |
Undercut and residual spacer prevention for dual stressed layers |
Jul. 17, 2007 |
| 7211197 |
Etching method and plasma processing method |
May. 1, 2007 |
| 7208419 |
Method for fabricating semiconductor device |
Apr. 24, 2007 |
| 7192894 |
High performance CMOS transistors using PMD liner stress |
Mar. 20, 2007 |
| 7172960 |
Multi-layer film stack for extinction of substrate reflections during patterning |
Feb. 6, 2007 |
| 7166232 |
Method for producing a solid body including a microstructure |
Jan. 23, 2007 |
| 7153778 |
Methods of forming openings, and methods of forming container capacitors |
Dec. 26, 2006 |
| 7148143 |
Semiconductor device having a fully silicided gate electrode and method of manufacture therefor |
Dec. 12, 2006 |
| 7141460 |
Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers |
Nov. 28, 2006 |
| 7119006 |
Via formation for damascene metal conductors in an integrated circuit |
Oct. 10, 2006 |
| 7115450 |
Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask |
Oct. 3, 2006 |
| 7084072 |
Method of manufacturing semiconductor device |
Aug. 1, 2006 |
| 7064075 |
Method for manufacturing semiconductor electronics devices |
Jun. 20, 2006 |
| 7060629 |
Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
Jun. 13, 2006 |
| 7049244 |
Method for enhancing silicon dioxide to silicon nitride selectivity |
May. 23, 2006 |
| 7045408 |
Integrated circuit with improved channel stress properties and a method for making it |
May. 16, 2006 |
| 7045464 |
Via reactive ion etching process |
May. 16, 2006 |
| 7041567 |
Isolation structure for trench capacitors and fabrication method thereof |
May. 9, 2006 |
| 7018944 |
Apparatus and method for nanoscale pattern generation |
Mar. 28, 2006 |
| 7005380 |
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer |
Feb. 28, 2006 |
| 6974989 |
Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing |
Dec. 13, 2005 |
| 6967170 |
Methods of forming silicon nitride spacers, and methods of forming dielectric sidewall spacers |
Nov. 22, 2005 |
| 6967167 |
Silicon dioxide removing method |
Nov. 22, 2005 |
| 6962879 |
Method of plasma etching silicon nitride |
Nov. 8, 2005 |
| 6960529 |
Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition |
Nov. 1, 2005 |
| 6960535 |
Dual damascene etching process |
Nov. 1, 2005 |
| 6958296 |
CVD TiSiN barrier for copper integration |
Oct. 25, 2005 |
| 6943092 |
Methods of manufacturing semiconductor devices |
Sep. 13, 2005 |
| 6939797 |
Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
Sep. 6, 2005 |
| 6933236 |
Method for forming pattern using argon fluoride photolithography |
Aug. 23, 2005 |
| 6927134 |
Method of forming a trench transistor having a superior gate dielectric |
Aug. 9, 2005 |
| 6913990 |
Method of forming isolation dummy fill structures |
Jul. 5, 2005 |
| 6908852 |
Method of forming an arc layer for a semiconductor device |
Jun. 21, 2005 |
| 6905943 |
Forming a trench to define one or more isolation regions in a semiconductor structure |
Jun. 14, 2005 |
| 6878612 |
Self-aligned contact process for semiconductor device |
Apr. 12, 2005 |
| 6875688 |
Method for reactive ion etch processing of a dual damascene structure |
Apr. 5, 2005 |
| 6869542 |
Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials |
Mar. 22, 2005 |
| 6852472 |
Polysilicon hard mask etch defect particle removal |
Feb. 8, 2005 |
| 6838369 |
Method for forming contact hole of semiconductor device |
Jan. 4, 2005 |
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