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Class Information
Number: 438/706
Name: Semiconductor device manufacturing: process > Chemical etching > Vapor phase etching (i.e., dry etching)
Description: Processes wherein the chemical etchant is in a gaseous state when brought into contact with the semiconductive substrate.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6294476 |
Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough |
Sep. 25, 2001 |
| 6290859 |
Tungsten coating for improved wear resistance and reliability of microelectromechanical devices |
Sep. 18, 2001 |
| 6291137 |
Sidewall formation for sidewall patterning of sub 100 nm structures |
Sep. 18, 2001 |
| 6291355 |
Method of fabricating a self-aligned contact opening |
Sep. 18, 2001 |
| 6287971 |
Method for forming a cell capacitor in DRAM device |
Sep. 11, 2001 |
| 6287973 |
Method for forming interconnection structure |
Sep. 11, 2001 |
| 6287974 |
Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
Sep. 11, 2001 |
| 6284661 |
Method and apparatus for producing a wafer |
Sep. 4, 2001 |
| 6284662 |
Method of forming a cobalt silicide layer by use of a TEOS through oxide film for ion-implantation process |
Sep. 4, 2001 |
| 6284663 |
Method for making field effect devices and capacitors with thin film dielectrics and resulting devices |
Sep. 4, 2001 |
| 6280645 |
Wafer flattening process and system |
Aug. 28, 2001 |
| 6280646 |
Use of a chemically active reticle carrier for photomask etching |
Aug. 28, 2001 |
| 6281132 |
Device and method for etching nitride spacers formed upon an integrated circuit gate conductor |
Aug. 28, 2001 |
| 6281133 |
Method for forming an inter-layer dielectric layer |
Aug. 28, 2001 |
| 6281134 |
Method for combining logic circuit and capacitor |
Aug. 28, 2001 |
| 6277657 |
Apparatus for fabricating semiconductor device and fabrication method therefor |
Aug. 21, 2001 |
| 6277720 |
Silicon nitride dopant diffusion barrier in integrated circuits |
Aug. 21, 2001 |
| 6277747 |
Method for removal of etch residue immediately after etching a SOG layer |
Aug. 21, 2001 |
| 6277752 |
Multiple etch method for forming residue free patterned hard mask layer |
Aug. 21, 2001 |
| 6277757 |
Methods to modify wet by dry etched via profile |
Aug. 21, 2001 |
| 6277758 |
Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher |
Aug. 21, 2001 |
| 6277759 |
Plasma etching methods |
Aug. 21, 2001 |
| 6277760 |
Method for fabricating ferroelectric capacitor |
Aug. 21, 2001 |
| 6274471 |
Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique |
Aug. 14, 2001 |
| 6274493 |
Method for forming a via |
Aug. 14, 2001 |
| 6274500 |
Single wafer in-situ dry clean and seasoning for plasma etching process |
Aug. 14, 2001 |
| 6274506 |
Apparatus and method for dispensing processing fluid toward a substrate surface |
Aug. 14, 2001 |
| 6271144 |
Process for etching a polycrystalline Si(1-x)Ge(x) layer or a stack of polycrystalline Si(1-x)Ge(x) layer and of a polycrystalline Si layer, and its application to microelectronics |
Aug. 7, 2001 |
| 6271145 |
Method for making a micromachine |
Aug. 7, 2001 |
| 6267076 |
Gas phase planarization process for semiconductor wafers |
Jul. 31, 2001 |
| 6268226 |
Reactive ion etch loading measurement technique |
Jul. 31, 2001 |
| 6268292 |
Methods for use in formation of titanium nitride interconnects |
Jul. 31, 2001 |
| 6268293 |
Method of forming wires on an integrated circuit chip |
Jul. 31, 2001 |
| 6268294 |
Method of protecting a low-K dielectric material |
Jul. 31, 2001 |
| 6265320 |
Method of minimizing reactive ion etch damage of organic insulating layers in semiconductor fabrication |
Jul. 24, 2001 |
| 6261965 |
Effective removal of undesirably formed silicon carbide during the manufacture of semiconductor device |
Jul. 17, 2001 |
| 6261966 |
Method for improving trench isolation |
Jul. 17, 2001 |
| 6258637 |
Method for thin film deposition on single-crystal semiconductor substrates |
Jul. 10, 2001 |
| 6258722 |
Method of manufacturing CMOS device |
Jul. 10, 2001 |
| 6258723 |
Dry etching method and a TFT fabrication method |
Jul. 10, 2001 |
| 6255127 |
Analyzing method and apparatus for minute foreign substances, and manufacturing methods for manufacturing semiconductor device and liquid crystal display device using the same |
Jul. 3, 2001 |
| 6251784 |
Real-time control of chemical-mechanical polishing processing by monitoring ionization current |
Jun. 26, 2001 |
| 6245192 |
Gas distribution apparatus for semiconductor processing |
Jun. 12, 2001 |
| 6245684 |
Method of obtaining a rounded top trench corner for semiconductor trench etch applications |
Jun. 12, 2001 |
| 6242352 |
Method of preventing micro-scratches on the surface of a semiconductor wafer when performing a CMP process |
Jun. 5, 2001 |
| 6242357 |
Method for forming a deep trench capacitor of a DRAM cell |
Jun. 5, 2001 |
| 6242358 |
Method for etching metal film containing aluminum and method for forming interconnection line of semiconductor device using the same |
Jun. 5, 2001 |
| 6242362 |
Etch process for fabricating a vertical hard mask/conductive pattern profile to improve T-shaped profile for a silicon oxynitride hard mask |
Jun. 5, 2001 |
| 6239006 |
Native oxide removal with fluorinated chemistry before cobalt silicide formation |
May. 29, 2001 |
| 6239034 |
Method of manufacturing inter-metal dielectric layers for semiconductor devices |
May. 29, 2001 |
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