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Class Information
Number: 438/703
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Plural coating steps
Description: Processes having multiple material deposition steps.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
7033948 Method for reducing dimensions between patterns on a photoresist Apr. 25, 2006
7015147 Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si.sub.1-xGe.sub.x layer Mar. 21, 2006
6979652 Etching multi-shaped openings in silicon Dec. 27, 2005
6939805 Method of etching a layer in a trench and method of fabricating a trench capacitor Sep. 6, 2005
6913701 Method for fabricating integrated LC/ESI device using SMILE, latent masking, and delayed LOCOS techniques Jul. 5, 2005
6911397 Method of forming dual damascene interconnection using low-k dielectric Jun. 28, 2005
6903031 In-situ-etch-assisted HDP deposition using SiF4 and hydrogen Jun. 7, 2005
6902656 Fabrication of microstructures with vacuum-sealed cavity Jun. 7, 2005
6900134 Method for forming openings in a substrate using bottom antireflective coatings May. 31, 2005
6900133 Method of etching variable depth features in a crystalline substrate May. 31, 2005
6887792 Embossed mask lithography May. 3, 2005
6878585 Methods of forming capacitors Apr. 12, 2005
6875688 Method for reactive ion etch processing of a dual damascene structure Apr. 5, 2005
6872633 Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to .ltoreq.0.10 microns Mar. 29, 2005
6867142 Method to prevent electrical shorts between tungsten interconnects Mar. 15, 2005
6867141 Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma Mar. 15, 2005
6867126 Method to increase cracking threshold for low-k materials Mar. 15, 2005
6864179 Semiconductor memory device having COB structure and method of fabricating the same Mar. 8, 2005
6864152 Fabrication of trenches with multiple depths on the same substrate Mar. 8, 2005
6855627 Method of using amorphous carbon to prevent resist poisoning Feb. 15, 2005
6846750 High precision pattern forming method of manufacturing a semiconductor device Jan. 25, 2005
6841465 Method of forming dual damascene pattern in semiconductor device Jan. 11, 2005
6828238 Methods of forming openings extending through electrically insulative material to electrically conductive material Dec. 7, 2004
6828186 Vertical sidewall profile spacer layer and method for fabrication thereof Dec. 7, 2004
6825129 Method for manufacturing memory device Nov. 30, 2004
6812115 Method of filling an opening in a material layer with an insulating material Nov. 2, 2004
6803314 Double-layered low dielectric constant dielectric dual damascene method Oct. 12, 2004
6797628 Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry Sep. 28, 2004
6784077 Shallow trench isolation process Aug. 31, 2004
6780770 Method for stacking semiconductor die within an implanted medical device Aug. 24, 2004
6774005 Method for fabricating a metal carbide layer and method for fabricating a trench capacitor containing a metal carbide Aug. 10, 2004
6774042 Planarization method for deep sub micron shallow trench isolation process Aug. 10, 2004
6770575 Method for improving thermal stability of fluorinated amorphous carbon low dielectric constant materials Aug. 3, 2004
6764949 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Jul. 20, 2004
6759336 Methods for reducing contamination of semiconductor substrates Jul. 6, 2004
6759332 Method for producing dual damascene interconnections and structure produced thereby Jul. 6, 2004
6756314 Method for etching a hard mask layer and a metal layer Jun. 29, 2004
6753256 Method of manufacturing semiconductor wafer Jun. 22, 2004
6750150 Method for reducing dimensions between patterns on a photoresist Jun. 15, 2004
6743727 Method of etching high aspect ratio openings Jun. 1, 2004
6740594 Method for removing carbon-containing polysilane from a semiconductor without stripping May. 25, 2004
6734109 Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon May. 11, 2004
6734107 Pitch reduction in semiconductor fabrication May. 11, 2004
6730605 Redistribution of copper deposited films May. 4, 2004
6713396 Method of fabricating high density sub-lithographic features on a substrate Mar. 30, 2004
6713393 Method of forming a nanometer-gate MOSFET device Mar. 30, 2004
6709984 Method for manufacturing semiconductor device Mar. 23, 2004
6706637 Dual damascene aperture formation method absent intermediate etch stop layer Mar. 16, 2004
6706634 Control of separation between transfer gate and storage node in vertical DRAM Mar. 16, 2004
6699794 Self aligned buried plate Mar. 2, 2004

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