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Class Information
Number: 438/703
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Plural coating steps
Description: Processes having multiple material deposition steps.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7351660 |
Process for producing high performance interconnects |
Apr. 1, 2008 |
| 7344974 |
Metallization method of semiconductor device |
Mar. 18, 2008 |
| 7344990 |
Method of manufacturing micro-structure element by utilizing molding glass |
Mar. 18, 2008 |
| 7341950 |
Method for controlling a thickness of a first layer and method for adjusting the thickness of different first layers |
Mar. 11, 2008 |
| 7335579 |
Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making |
Feb. 26, 2008 |
| 7329586 |
Gapfill using deposition-etch sequence |
Feb. 12, 2008 |
| 7316978 |
Method for forming recesses |
Jan. 8, 2008 |
| 7307014 |
Method of forming a via contact structure using a dual damascene process |
Dec. 11, 2007 |
| 7307024 |
Flash memory and fabrication method thereof |
Dec. 11, 2007 |
| 7303995 |
Method for reducing dimensions between patterns on a photoresist |
Dec. 4, 2007 |
| 7282434 |
Method of manufacturing a semiconductor device |
Oct. 16, 2007 |
| 7279396 |
Methods of forming trench isolation regions with nitride liner |
Oct. 9, 2007 |
| 7262118 |
Method for generating a structure on a substrate |
Aug. 28, 2007 |
| 7253112 |
Dual damascene process |
Aug. 7, 2007 |
| 7253113 |
Methods for using a silylation technique to reduce cell pitch in semiconductor devices |
Aug. 7, 2007 |
| 7247582 |
Deposition of tensile and compressive stressed materials |
Jul. 24, 2007 |
| 7244680 |
Method of simultaneously fabricating isolation structures having rounded and unrounded corners |
Jul. 17, 2007 |
| 7232764 |
Semiconductor device fabrication method |
Jun. 19, 2007 |
| 7217625 |
Method of fabricating a semiconductor device having a shallow source/drain region |
May. 15, 2007 |
| 7217663 |
Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof |
May. 15, 2007 |
| 7205244 |
Patterning substrates employing multi-film layers defining etch-differential interfaces |
Apr. 17, 2007 |
| 7189628 |
Fabrication of trenches with multiple depths on the same substrate |
Mar. 13, 2007 |
| 7183218 |
Methods for fabricating a semiconductor device with etch end point detection |
Feb. 27, 2007 |
| 7179748 |
Method for forming recesses |
Feb. 20, 2007 |
| 7172975 |
Process for the wet chemical treatment of semiconductor wafers |
Feb. 6, 2007 |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
Jan. 30, 2007 |
| 7153753 |
Strained Si/SiGe/SOI islands and processes of making same |
Dec. 26, 2006 |
| 7153778 |
Methods of forming openings, and methods of forming container capacitors |
Dec. 26, 2006 |
| 7141485 |
Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
Nov. 28, 2006 |
| 7129177 |
Write head fabrication by inverting order of process steps |
Oct. 31, 2006 |
| 7112484 |
Thin film diode integrated with chalcogenide memory cell |
Sep. 26, 2006 |
| 7109121 |
Stress control of semiconductor microstructures for thin film growth |
Sep. 19, 2006 |
| 7109119 |
Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
Sep. 19, 2006 |
| 7105453 |
Method for forming contact holes |
Sep. 12, 2006 |
| 7084072 |
Method of manufacturing semiconductor device |
Aug. 1, 2006 |
| 7083898 |
Method for performing chemical shrink process over BARC (bottom anti-reflective coating) |
Aug. 1, 2006 |
| 7074668 |
Capacitor of semiconductor device and method for forming the same |
Jul. 11, 2006 |
| 7071109 |
Methods for fabricating spatial light modulators with hidden comb actuators |
Jul. 4, 2006 |
| 7067429 |
Processing method of forming MRAM circuitry |
Jun. 27, 2006 |
| RE39143 |
Method for making a wafer-pair having sealed chambers |
Jun. 27, 2006 |
| 7060622 |
Method of forming dummy wafer |
Jun. 13, 2006 |
| 7052977 |
Method of dicing a semiconductor wafer that substantially reduces the width of the saw street |
May. 30, 2006 |
| 7033948 |
Method for reducing dimensions between patterns on a photoresist |
Apr. 25, 2006 |
| 7015147 |
Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si.sub.1-xGe.sub.x layer |
Mar. 21, 2006 |
| 6979652 |
Etching multi-shaped openings in silicon |
Dec. 27, 2005 |
| 6939805 |
Method of etching a layer in a trench and method of fabricating a trench capacitor |
Sep. 6, 2005 |
| 6913701 |
Method for fabricating integrated LC/ESI device using SMILE, latent masking, and delayed LOCOS techniques |
Jul. 5, 2005 |
| 6911397 |
Method of forming dual damascene interconnection using low-k dielectric |
Jun. 28, 2005 |
| 6903031 |
In-situ-etch-assisted HDP deposition using SiF4 and hydrogen |
Jun. 7, 2005 |
| 6902656 |
Fabrication of microstructures with vacuum-sealed cavity |
Jun. 7, 2005 |
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