Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Engineering
Class Information
Number: 438/702
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Plural coating steps
Description: Processes wherein the viahole or trench is formed by a process having multiple material deposition steps.


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
5578524 Fabrication process of a semiconductor device with a wiring structure Nov. 26, 1996
5569355 Method for fabrication of microchannel electron multipliers Oct. 29, 1996
5567270 Process of forming contacts and vias having tapered sidewall Oct. 22, 1996
5567659 Method of etching patterns in III-V material with accurate depth control Oct. 22, 1996
5565384 Self-aligned via using low permittivity dielectric Oct. 15, 1996
5565376 Device isolation technology by liquid phase deposition Oct. 15, 1996
5563102 Method of sealing integrated circuits Oct. 8, 1996
5559058 Method for producing native oxides on compound semiconductors Sep. 24, 1996
5554256 Method of manufacturing a semiconductor device having a semiconductor body with field insulation regions formed by grooves filled with insulating material Sep. 10, 1996
5552344 Non-etchback self-aligned via size reduction method employing ozone assisted chemical vapor deposited silicon oxide Sep. 3, 1996
5543013 Method of forming a microstructure with bare silicon ground plane Aug. 6, 1996
5538592 Non-random sub-lithography vertical stack capacitor Jul. 23, 1996
5538592 Non-random sub-lithography vertical stack capacitor Jul. 23, 1996
5512513 Method of fabricating semiconductor device with water protective film Apr. 30, 1996
5510286 Method for forming narrow contact holes of a semiconductor device Apr. 23, 1996
5500080 Process of forming contact holes Mar. 19, 1996
5498570 Method of reducing overetch during the formation of a semiconductor device Mar. 12, 1996
5488011 Method of forming contact areas between vertical conductors Jan. 30, 1996
5482882 Method for forming most capacitor using polysilicon islands Jan. 9, 1996
5478438 Method of etching semiconductor substrate Dec. 26, 1995
5478460 Electrolyte composition for screen printing and miniaturized oxygen electrode and production process thereof Dec. 26, 1995
5476807 Method for forming fine patterns in a semiconductor device Dec. 19, 1995
5472885 Method of producing solar cell Dec. 5, 1995
5472562 Method of etching silicon nitride Dec. 5, 1995
5472913 Method of fabricating porous dielectric material with a passivation layer for electronics applications Dec. 5, 1995
5470797 Method for producing a silicon-on-insulator capacitive surface micromachined absolute pressure sensor Nov. 28, 1995
5466640 Method for forming a metal wire of a semiconductor device Nov. 14, 1995
5466640 Method for forming a metal wire of a semiconductor device Nov. 14, 1995
5466630 Silicon-on-insulator technique with buried gap Nov. 14, 1995
5466630 Silicon-on-insulator technique with buried gap Nov. 14, 1995
5459095 Method for making capacitor for use in DRAM cell using triple layers of photoresist Oct. 17, 1995
5459086 Metal via sidewall tilt angle implant for SOG Oct. 17, 1995
5457073 Multi-level interconnection CMOS devices with SOG Oct. 10, 1995
5453157 Low temperature anisotropic ashing of resist for semiconductor fabrication Sep. 26, 1995
5451543 Straight sidewall profile contact opening to underlying interconnect and method for making the same Sep. 19, 1995
5451541 Method for fabricating a semiconductor device Sep. 19, 1995
5451291 Method for forming a via contact hole of a semiconductor device Sep. 19, 1995
5449644 Process for contact hole formation using a sacrificial SOG layer Sep. 12, 1995
5447884 Shallow trench isolation with thin nitride liner Sep. 5, 1995
5444021 Method for making a contact hole of a semiconductor device Aug. 22, 1995
5437763 Method for formation of contact vias in integrated circuits Aug. 1, 1995
5438023 Passivation method and structure for a ferroelectric integrated circuit using hard ceramic materials or the like Aug. 1, 1995
5436188 Dram cell process having elk horn shaped capacitor Jul. 25, 1995
5433823 Selective dry-etching of bi-layer passivation films Jul. 18, 1995
5434109 Oxidation of silicon nitride in semiconductor devices Jul. 18, 1995
5432113 Method of making a semiconductor memory device Jul. 11, 1995
5429993 Semiconductor accelerometer and method of its manufacture Jul. 4, 1995
5429990 Spin-on-glass planarization process with ion implantation Jul. 4, 1995
5427975 Method of micromachining an integrated sensor on the surface of a silicon wafer Jun. 27, 1995
5425845 Method for selective removal of hard trench masks Jun. 20, 1995

1 2 3 4 5 6 7 8 9 10 11 12 13


 
 
  Recently Added Patents
Process for preparing polyethylene
Critical area computation of composite fault mechanisms using Voronoi diagrams
Light-emitting diode (LED)
Method for preventing a stationary vehicle from unintentionally rolling
Precision capacitor array
Steam cracking of hydrocarbon feedstocks containing salt and/or particulate matter
Power supply devices with illuminated receptacles
  Randomly Featured Patents
Magnetic suspension and pointing system
Noble metal supported on a base metal catalyst
Dipper and mixer driveway and roof spreader brush
Capacitor-coupled bipolar active pixel sensor with integrated electronic shutter
Multichannel magnetic and optical linear head
Photosensitive microcapsules useful in polychromatic imaging having radiation absorber
Coin validator with optical coupling
1-[2-(Alkyl and arylsulfonyl)-2-propenyl and propyl] substituted piperidines useful as antimicrobial and antiinflammatory agents
Filling system for hermetically sealed batteries
Integrated low-k hard mask