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Class Information
Number: 438/702
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Plural coating steps
Description: Processes wherein the viahole or trench is formed by a process having multiple material deposition steps.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6239478 |
Semiconductor structure for a MOS transistor |
May. 29, 2001 |
| 6235593 |
Self aligned contact using spacers on the ILD layer sidewalls |
May. 22, 2001 |
| 6232141 |
Semiconductor light-receiving device and method of fabricating the same |
May. 15, 2001 |
| 6228768 |
Storage-annealing plated CU interconnects |
May. 8, 2001 |
| 6225227 |
Method for manufacturing semiconductor device |
May. 1, 2001 |
| 6221734 |
Method of reducing CMP dishing effect |
Apr. 24, 2001 |
| 6221780 |
Dual damascene flowable oxide insulation structure and metallic barrier |
Apr. 24, 2001 |
| 6221778 |
Method of fabricating a semiconductor device |
Apr. 24, 2001 |
| 6207555 |
Electron beam process during dual damascene processing |
Mar. 27, 2001 |
| 6203863 |
Method of gap filling |
Mar. 20, 2001 |
| 6204187 |
Contact and deep trench patterning |
Mar. 20, 2001 |
| 6200900 |
Method for formation of an air gap in an integrated circuit architecture |
Mar. 13, 2001 |
| 6200902 |
Method of etching a layer in a semiconductor device |
Mar. 13, 2001 |
| 6200653 |
Method of forming an intermetal dielectric layer |
Mar. 13, 2001 |
| 6197682 |
Structure of a contact hole in a semiconductor device and method of manufacturing the same |
Mar. 6, 2001 |
| 6194318 |
Manufacturing multiple layered structures of large scale integrated semiconductor devices |
Feb. 27, 2001 |
| 6191029 |
Damascene process |
Feb. 20, 2001 |
| 6187671 |
Method of forming semiconductor device having minute contact hole |
Feb. 13, 2001 |
| 6180516 |
Method of fabricating a dual damascene structure |
Jan. 30, 2001 |
| 6169021 |
Method of making a metallized recess in a substrate |
Jan. 2, 2001 |
| 6159842 |
Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections |
Dec. 12, 2000 |
| 6159844 |
Fabrication of gate and diffusion contacts in self-aligned contact process |
Dec. 12, 2000 |
| 6156664 |
Method of manufacturing liner insulating layer |
Dec. 5, 2000 |
| 6153527 |
Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material |
Nov. 28, 2000 |
| 6136637 |
Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide |
Oct. 24, 2000 |
| 6117734 |
Method of forming a trench MOS gate on a power semiconductor device |
Sep. 12, 2000 |
| 6110827 |
Planarization method for self-aligned contact process |
Aug. 29, 2000 |
| 6110798 |
Method of fabricating an isolation structure on a semiconductor substrate |
Aug. 29, 2000 |
| 6107143 |
Method for forming a trench isolation structure in an integrated circuit |
Aug. 22, 2000 |
| 6103545 |
Process for making a magnetoresistive magnetic sensor and sensor obtained using this process |
Aug. 15, 2000 |
| 6103595 |
Assisted local oxidation of silicon |
Aug. 15, 2000 |
| 6100200 |
Sputtering process for the conformal deposition of a metallization or insulating layer |
Aug. 8, 2000 |
| 6100109 |
Method for producing a memory device |
Aug. 8, 2000 |
| 6096656 |
Formation of microchannels from low-temperature plasma-deposited silicon oxynitride |
Aug. 1, 2000 |
| 6096655 |
Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure |
Aug. 1, 2000 |
| 6087263 |
Methods of forming integrated circuitry and integrated circuitry structures |
Jul. 11, 2000 |
| 6087251 |
Method of fabricating a dual damascene structure |
Jul. 11, 2000 |
| 6087197 |
Aggregate of semiconductor micro-needles and method of manufacturing the same, and semiconductor apparatus and method of manufacturing the same |
Jul. 11, 2000 |
| 6080661 |
Methods for fabricating gate and diffusion contacts in self-aligned contact processes |
Jun. 27, 2000 |
| 6071794 |
Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator |
Jun. 6, 2000 |
| 6059983 |
Method for fabricating an overcoated printed circuit board with contaminant-free areas |
May. 9, 2000 |
| 6057211 |
Method for manufacturing an integrated circuit arrangement |
May. 2, 2000 |
| 6057241 |
Method of manufacturing a semiconductor integrated circuit device |
May. 2, 2000 |
| 6051501 |
Method of reducing overetch during the formation of a semiconductor device |
Apr. 18, 2000 |
| 6051497 |
Formation of sub-groundrule features |
Apr. 18, 2000 |
| 6045712 |
Micromachined reflector antenna method |
Apr. 4, 2000 |
| 6043160 |
Method of manufacturing a monitor pad for chemical mechanical polishing planarization |
Mar. 28, 2000 |
| 6040231 |
Method of fabricating a shallow trench isolation structure which includes using a salicide process to form an aslope periphery at the top corner of the substrate |
Mar. 21, 2000 |
| 6037262 |
Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure |
Mar. 14, 2000 |
| 6037261 |
Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material |
Mar. 14, 2000 |
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