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Class Information
Number: 438/702
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Plural coating steps
Description: Processes wherein the viahole or trench is formed by a process having multiple material deposition steps.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6548406 |
Method for forming integrated circuit having MONOS device and mixed-signal circuit |
Apr. 15, 2003 |
| 6548397 |
Electrical and thermal contact for use in semiconductor devices |
Apr. 15, 2003 |
| 6538328 |
Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant |
Mar. 25, 2003 |
| 6537733 |
Method of depositing low dielectric constant silicon carbide layers |
Mar. 25, 2003 |
| 6537914 |
Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing |
Mar. 25, 2003 |
| 6534410 |
Method for forming conductor members, manufacturing method of semiconductor element and manufacturing method of thin-film magnetic head |
Mar. 18, 2003 |
| 6531067 |
Method for forming contact hole |
Mar. 11, 2003 |
| 6531331 |
Monolithic integration of a MOSFET with a MEMS device |
Mar. 11, 2003 |
| 6509274 |
Method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate |
Jan. 21, 2003 |
| 6503818 |
Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material |
Jan. 7, 2003 |
| 6503840 |
Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning |
Jan. 7, 2003 |
| 6498105 |
Method of forming fine patterns of a semiconductor device |
Dec. 24, 2002 |
| 6495395 |
Electrical and thermal contact for use in semiconductor devices |
Dec. 17, 2002 |
| 6479369 |
Shallow trench isolation (STI) and method of forming the same |
Nov. 12, 2002 |
| 6472307 |
Methods for improved encapsulation of thick metal features in integrated circuit fabrication |
Oct. 29, 2002 |
| 6461966 |
Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement |
Oct. 8, 2002 |
| 6444524 |
Method for forming a trench capacitor |
Sep. 3, 2002 |
| 6436836 |
Method of fabricating a DRAM cell configuration |
Aug. 20, 2002 |
| 6420272 |
Method for removal of hard mask used to define noble metal electrode |
Jul. 16, 2002 |
| 6417071 |
Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity |
Jul. 9, 2002 |
| 6410452 |
Method of manufacturing semiconductor device |
Jun. 25, 2002 |
| 6410106 |
Method of forming an intermetal dielectric layer |
Jun. 25, 2002 |
| 6392269 |
Non-volatile semiconductor memory and manufacturing method thereof |
May. 21, 2002 |
| 6391784 |
Spacer-assisted ultranarrow shallow trench isolation formation |
May. 21, 2002 |
| 6383936 |
Method for removing black silicon in semiconductor fabrication |
May. 7, 2002 |
| 6373115 |
Micromechanical structure, sensor and method for manufacturing the same |
Apr. 16, 2002 |
| 6365327 |
Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit |
Apr. 2, 2002 |
| 6352932 |
Methods of forming integrated circuitry and integrated circuitry structures |
Mar. 5, 2002 |
| 6350695 |
Pillar process for copper interconnect scheme |
Feb. 26, 2002 |
| 6348402 |
Method of manufacturing a copper interconnect |
Feb. 19, 2002 |
| 6345399 |
Hard mask process to prevent surface roughness for selective dielectric etching |
Feb. 12, 2002 |
| 6340435 |
Integrated low K dielectrics and etch stops |
Jan. 22, 2002 |
| 6339003 |
Method of fabricating a semiconductor device |
Jan. 15, 2002 |
| 6335289 |
Manufacturing method of semiconductor device |
Jan. 1, 2002 |
| 6333256 |
Semiconductor processing method of forming openings in a material |
Dec. 25, 2001 |
| 6326310 |
Method and system for providing shallow trench profile shaping through spacer and etching |
Dec. 4, 2001 |
| 6316349 |
Method for forming contacts of semiconductor devices |
Nov. 13, 2001 |
| 6309974 |
Method for eliminating residual oxygen impurities from silicon wafers pulled from a crucible |
Oct. 30, 2001 |
| 6309963 |
Method for manufacturing semiconductor device |
Oct. 30, 2001 |
| 6306699 |
Semiconductor device having conducting material film formed in trench, manufacturing method thereof and method of forming resist pattern used therein |
Oct. 23, 2001 |
| 6306769 |
Use of dual patterning masks for printing holes of small dimensions |
Oct. 23, 2001 |
| 6297130 |
Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS isolation methods |
Oct. 2, 2001 |
| 6284643 |
Electrical and thermal contact for use in semiconductor devices |
Sep. 4, 2001 |
| 6281090 |
Method for the manufacture of printed circuit boards with plated resistors |
Aug. 28, 2001 |
| 6261962 |
Method of surface treatment of semiconductor substrates |
Jul. 17, 2001 |
| 6258695 |
Dislocation suppression by carbon incorporation |
Jul. 10, 2001 |
| 6258722 |
Method of manufacturing CMOS device |
Jul. 10, 2001 |
| 6248668 |
Dendritic material sacrificial layer micro-scale gap formation method |
Jun. 19, 2001 |
| 6245636 |
Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate |
Jun. 12, 2001 |
| 6245683 |
Stress relieve pattern for damascene process |
Jun. 12, 2001 |
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