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Class Information
Number: 438/702
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Plural coating steps
Description: Processes wherein the viahole or trench is formed by a process having multiple material deposition steps.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7354523 |
Methods for sidewall etching and etching during filling of a trench |
Apr. 8, 2008 |
| 7344974 |
Metallization method of semiconductor device |
Mar. 18, 2008 |
| 7344995 |
Method for preparing a structure with high aspect ratio |
Mar. 18, 2008 |
| 7341950 |
Method for controlling a thickness of a first layer and method for adjusting the thickness of different first layers |
Mar. 11, 2008 |
| 7332399 |
Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled |
Feb. 19, 2008 |
| 7332409 |
Methods of forming trench isolation layers using high density plasma chemical vapor deposition |
Feb. 19, 2008 |
| 7323115 |
Substrate processing method and ink jet recording head substrate manufacturing method |
Jan. 29, 2008 |
| 7319076 |
Low resistance T-shaped ridge structure |
Jan. 15, 2008 |
| 7307015 |
Method for forming an interconnection line in a semiconductor device |
Dec. 11, 2007 |
| 7300878 |
Gas switching during an etch process to modulate the characteristics of the etch |
Nov. 27, 2007 |
| 7300882 |
Etching method and semiconductor device fabricating method |
Nov. 27, 2007 |
| 7279341 |
Method for fabricating a flux concentrating system for use in a magnetoelectronics device |
Oct. 9, 2007 |
| 7276448 |
Method for an integrated circuit contact |
Oct. 2, 2007 |
| 7271108 |
Multiple mask process with etch mask stack |
Sep. 18, 2007 |
| 7271107 |
Reduction of feature critical dimensions using multiple masks |
Sep. 18, 2007 |
| 7259102 |
Etching technique to planarize a multi-layer structure |
Aug. 21, 2007 |
| 7253112 |
Dual damascene process |
Aug. 7, 2007 |
| 7250371 |
Reduction of feature critical dimensions |
Jul. 31, 2007 |
| 7232764 |
Semiconductor device fabrication method |
Jun. 19, 2007 |
| 7217663 |
Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof |
May. 15, 2007 |
| 7205242 |
Method for forming isolation layer in semiconductor device |
Apr. 17, 2007 |
| 7202174 |
Method of forming micro pattern in semiconductor device |
Apr. 10, 2007 |
| 7192873 |
Method of manufacturing nano scale semiconductor device using nano particles |
Mar. 20, 2007 |
| 7189605 |
Method for fabricating semiconductor device |
Mar. 13, 2007 |
| 7183202 |
Method of forming metal wiring in a semiconductor device |
Feb. 27, 2007 |
| 7179758 |
Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics |
Feb. 20, 2007 |
| 7176039 |
Dynamic modification of gap fill process characteristics |
Feb. 13, 2007 |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
Jan. 30, 2007 |
| 7163883 |
Edge seal for a semiconductor device |
Jan. 16, 2007 |
| 7141485 |
Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
Nov. 28, 2006 |
| 7138338 |
Method and composite hard mask for forming deep trenches in a semiconductor substrate |
Nov. 21, 2006 |
| 7135380 |
Method for manufacturing semiconductor device |
Nov. 14, 2006 |
| 7132306 |
Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set |
Nov. 7, 2006 |
| 7125804 |
Etching methods and apparatus and substrate assemblies produced therewith |
Oct. 24, 2006 |
| 7112484 |
Thin film diode integrated with chalcogenide memory cell |
Sep. 26, 2006 |
| 7109119 |
Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
Sep. 19, 2006 |
| 7101804 |
Method for forming fuse integrated with dual damascene process |
Sep. 5, 2006 |
| 7083898 |
Method for performing chemical shrink process over BARC (bottom anti-reflective coating) |
Aug. 1, 2006 |
| 7078313 |
Method for fabricating an integrated semiconductor circuit to prevent formation of voids |
Jul. 18, 2006 |
| 7074668 |
Capacitor of semiconductor device and method for forming the same |
Jul. 11, 2006 |
| 7071094 |
Dual layer barrier film techniques to prevent resist poisoning |
Jul. 4, 2006 |
| 7071054 |
Methods of fabricating MIM capacitors in semiconductor devices |
Jul. 4, 2006 |
| 7067329 |
Methods of forming ferroelectric memory devices |
Jun. 27, 2006 |
| 7067429 |
Processing method of forming MRAM circuitry |
Jun. 27, 2006 |
| 7060567 |
Method for fabricating trench power MOSFET |
Jun. 13, 2006 |
| 7060625 |
Imprint stamp |
Jun. 13, 2006 |
| 7052998 |
Method of manufacturing photovoltaic device |
May. 30, 2006 |
| 7049240 |
Formation method of SiGe HBT |
May. 23, 2006 |
| 7041567 |
Isolation structure for trench capacitors and fabrication method thereof |
May. 9, 2006 |
| 7037841 |
Dual damascene interconnecting line structure and fabrication method thereof |
May. 2, 2006 |
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