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Class Information
Number: 438/701
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Tapered configuration
Description: Processes wherein the viahole or trench is formed so as to possess nonparallel sides.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 4816115 |
Process of making via holes in a double-layer insulation |
Mar. 28, 1989 |
| 4810557 |
Method of making an article comprising a tandem groove, and article produced by the method |
Mar. 7, 1989 |
| 4808260 |
Directional aperture etched in silicon |
Feb. 28, 1989 |
| 4807016 |
Dry etch of phosphosilicate glass with selectivity to undoped oxide |
Feb. 21, 1989 |
| 4784720 |
Trench etch process for a single-wafer RIE dry etch reactor |
Nov. 15, 1988 |
| 4776922 |
Formation of variable-width sidewall structures |
Oct. 11, 1988 |
| 4765864 |
Etching method for producing an electrochemical cell in a crystalline substrate |
Aug. 23, 1988 |
| 4764249 |
Method for producing a coating layer for semiconductor technology and also use of the coating layer |
Aug. 16, 1988 |
| 4758305 |
Contact etch method |
Jul. 19, 1988 |
| 4744858 |
Integrated circuit metallization with reduced electromigration |
May. 17, 1988 |
| 4728627 |
Method of making multilayered interconnects using hillock studs formed by sintering |
Mar. 1, 1988 |
| 4705597 |
Photoresist tapering process |
Nov. 10, 1987 |
| 4705596 |
Simultaneous plasma sculpturing and dual tapered aperture etch |
Nov. 10, 1987 |
| 4698128 |
Sloped contact etch process |
Oct. 6, 1987 |
| 4693781 |
Trench formation process |
Sep. 15, 1987 |
| 4681653 |
Planarized dielectric deposited using plasma enhanced chemical vapor deposition |
Jul. 21, 1987 |
| 4680615 |
Silicon semiconductor component with an edge contour made by an etching technique, and method for manufacturing this component |
Jul. 14, 1987 |
| 4676869 |
Integrated circuits having stepped dielectric regions |
Jun. 30, 1987 |
| 4675074 |
Method of manufacturing semiconductor device |
Jun. 23, 1987 |
| 4672354 |
Fabrication of dielectrically isolated fine line semiconductor transducers and apparatus |
Jun. 9, 1987 |
| 4656732 |
Integrated circuit fabrication process |
Apr. 14, 1987 |
| 4645562 |
Double layer photoresist technique for side-wall profile control in plasma etching processes |
Feb. 24, 1987 |
| RE32351 |
Method of manufacturing a passivating composite comprising a silicon nitride (SI.sub.1 3N.sub.4) layer and a phosphosilicate glass (PSG) layer for a semiconductor device layer |
Feb. 17, 1987 |
| 4641420 |
Metalization process for headless contact using deposited smoothing material |
Feb. 10, 1987 |
| 4639288 |
Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching |
Jan. 27, 1987 |
| 4634494 |
Etching of a phosphosilicate glass film selectively implanted with boron |
Jan. 6, 1987 |
| 4624740 |
Tailoring of via-hole sidewall slope |
Nov. 25, 1986 |
| 4605470 |
Method for interconnecting conducting layers of an integrated circuit device |
Aug. 12, 1986 |
| 4595454 |
Fabrication of grooved semiconductor devices |
Jun. 17, 1986 |
| 4563227 |
Method for manufacturing a semiconductor device |
Jan. 7, 1986 |
| 4560436 |
Process for etching tapered polyimide vias |
Dec. 24, 1985 |
| 4545851 |
Etching method for semiconductor devices |
Oct. 8, 1985 |
| 4543707 |
Method of forming through holes by differential etching of stacked silicon oxynitride layers |
Oct. 1, 1985 |
| 4542037 |
Laser induced flow of glass bonded materials |
Sep. 17, 1985 |
| 4534825 |
Method of making an electrochemical sensing cell |
Aug. 13, 1985 |
| 4528211 |
Silicon nitride formation and use in self-aligned semiconductor device manufacturing method |
Jul. 9, 1985 |
| 4523976 |
Method for forming semiconductor devices |
Jun. 18, 1985 |
| 4518629 |
Process for positioning an electrical contact hole between two interconnection lines of an integrated circuit |
May. 21, 1985 |
| 4517730 |
Method of providing a small-sized opening, use of this method for the manufacture of field effect transistors having an aligned gate in the submicron range and transistors thus obtained |
May. 21, 1985 |
| 4514251 |
Method of manufacturing a semiconductor device, in which patterns are formed in a layer of silicon nitride by means of ion implantation |
Apr. 30, 1985 |
| 4508815 |
Recessed metallization |
Apr. 2, 1985 |
| 4499653 |
Small dimension field effect transistor using phosphorous doped silicon glass reflow process |
Feb. 19, 1985 |
| 4495220 |
Polyimide inter-metal dielectric process |
Jan. 22, 1985 |
| 4487652 |
Slope etch of polyimide |
Dec. 11, 1984 |
| 4484978 |
Etching method |
Nov. 27, 1984 |
| 4476621 |
Process for making transistors with doped oxide densification |
Oct. 16, 1984 |
| 4472239 |
Method of making semiconductor device |
Sep. 18, 1984 |
| 4472240 |
Method for manufacturing semiconductor device |
Sep. 18, 1984 |
| 4470875 |
Fabrication of silicon devices requiring anisotropic etching |
Sep. 11, 1984 |
| 4455325 |
Method of inducing flow or densification of phosphosilicate glass for integrated circuits |
Jun. 19, 1984 |
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