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Class Information
Number: 438/701
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Tapered configuration
Description: Processes wherein the viahole or trench is formed so as to possess nonparallel sides.


Patents under this class:
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Patent Number Title Of Patent Date Issued
6037265 Etchant gas and a method for etching transistor gates Mar. 14, 2000
6025277 Method and structure for preventing bonding pad peel back Feb. 15, 2000
6010957 Semiconductor device having tapered conductive lines and fabrication thereof Jan. 4, 2000
6010953 Method for forming a semiconductor buried contact with a removable spacer Jan. 4, 2000
5998301 Method and system for providing tapered shallow trench isolation structure profile Dec. 7, 1999
5994220 Method for forming a semiconductor connection with a top surface having an enlarged recess Nov. 30, 1999
5994228 Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes Nov. 30, 1999
5989997 Method for forming dual damascene structure Nov. 23, 1999
5981397 Integrated circuitry having a pair of adjacent conductive lines and method of forming Nov. 9, 1999
5976985 Processing methods of forming contact openings and integrated circuitry Nov. 2, 1999
5946593 Semiconductor device manufacturing method Aug. 31, 1999
5940731 Method for forming tapered polysilicon plug and plug formed Aug. 17, 1999
5937309 Method for fabricating shallow trench isolation structure Aug. 10, 1999
5933755 Method of fabricating contact sites for microelectronic devices Aug. 3, 1999
5933715 Process for manufacturing discrete electronic devices Aug. 3, 1999
5930644 Method of forming a shallow trench isolation using oxide slope etching Jul. 27, 1999
5926735 Method of forming semiconductor device Jul. 20, 1999
5926725 Method of manufacturing semiconductor devices with a reverse tapered sectional configuration Jul. 20, 1999
5920781 Method of making semiconductor device Jul. 6, 1999
5914189 Protected thermal barrier coating composite with multiple coatings Jun. 22, 1999
5913148 Reduced size etching method for integrated circuits Jun. 15, 1999
5912185 Methods for forming contact holes having improved sidewall profiles Jun. 15, 1999
5897374 Vertical via/contact with undercut dielectric Apr. 27, 1999
5895271 Metal film forming method Apr. 20, 1999
5895253 Trench isolation for CMOS devices Apr. 20, 1999
5895937 Tapered dielectric etch in semiconductor devices Apr. 20, 1999
5893757 Tapered profile etching method Apr. 13, 1999
5891771 Recessed structure for shallow trench isolation and salicide process Apr. 6, 1999
5883002 Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device Mar. 16, 1999
5882968 Semiconductor device fabrication method Mar. 16, 1999
5882982 Trench isolation method Mar. 16, 1999
5880030 Unlanded via structure and method for making same Mar. 9, 1999
5880019 Insitu contact descum for self-aligned contact process Mar. 9, 1999
5880005 Method for forming a tapered profile insulator shape Mar. 9, 1999
5880004 Trench isolation process Mar. 9, 1999
5874358 Via hole profile and method of fabrication Feb. 23, 1999
5864180 Semiconductor device and method for manufacturing the same Jan. 26, 1999
5858859 Semiconductor device having a trench for device isolation fabrication method Jan. 12, 1999
5858824 Method of forming fine electrode on semiconductor substrate Jan. 12, 1999
5854140 Method of making an aluminum contact Dec. 29, 1998
5854509 Method of fabricating semiconductor device and semiconductor device Dec. 29, 1998
5849611 Method for forming a taper shaped contact hole by oxidizing a wiring Dec. 15, 1998
5841195 Semiconductor contact via structure Nov. 24, 1998
5807789 Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) Sep. 15, 1998
5801083 Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners Sep. 1, 1998
5795814 Method for manufacturing semiconductor device having groove-type isolation area Aug. 18, 1998
5795823 Self aligned via dual damascene Aug. 18, 1998
5795825 Connection layer forming method Aug. 18, 1998
5786632 Semiconductor package Jul. 28, 1998
5767019 Method for forming a fine contact hole in a semiconductor device Jun. 16, 1998

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