| Patent Number |
Title Of Patent |
Date Issued |
| 6287962 |
Method for making a novel graded silicon nitride/silicon oxide (SNO) hard mask for improved deep sub-micrometer semiconductor processing |
Sep. 11, 2001 |
| 6277731 |
Method for forming a semiconductor connection with a top surface having an enlarged recess |
Aug. 21, 2001 |
| 6274483 |
Method to improve metal line adhesion by trench corner shape modification |
Aug. 14, 2001 |
| 6274457 |
Method for manufacturing an isolation trench having plural profile angles |
Aug. 14, 2001 |
| 6265292 |
Method of fabrication of a novel flash integrated circuit |
Jul. 24, 2001 |
| 6261968 |
Method of forming a self-aligned contact hole on a semiconductor wafer |
Jul. 17, 2001 |
| 6258701 |
Process for forming insulating structures for integrated circuits |
Jul. 10, 2001 |
| 6258711 |
Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers |
Jul. 10, 2001 |
| 6242344 |
Tri-layer resist method for dual damascene process |
Jun. 5, 2001 |
| 6242275 |
Method for manufacturing quantum wires |
Jun. 5, 2001 |
| 6239019 |
Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics |
May. 29, 2001 |
| 6235561 |
Method of manufacturing thin-film transistors |
May. 22, 2001 |
| 6232203 |
Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches |
May. 15, 2001 |
| 6228769 |
Endpoint detection by chemical reaction and photoionization |
May. 8, 2001 |
| 6228754 |
Method for forming semiconductor seed layers by inert gas sputter etching |
May. 8, 2001 |
| 6221734 |
Method of reducing CMP dishing effect |
Apr. 24, 2001 |
| 6204186 |
Method of making integrated circuit capacitor including tapered plug |
Mar. 20, 2001 |
| 6204191 |
Method of manufacturing semiconductor devices and semiconductor device capacitor manufactured thereby |
Mar. 20, 2001 |
| 6200880 |
Method for forming shallow trench isolation |
Mar. 13, 2001 |
| 6194236 |
Electrochemical etching method for silicon substrate having PN junction |
Feb. 27, 2001 |
| 6180516 |
Method of fabricating a dual damascene structure |
Jan. 30, 2001 |
| 6180440 |
Method of fabricating a recessed-gate FET without producing voids in the gate metal |
Jan. 30, 2001 |
| 6177331 |
Method for manufacturing semiconductor device |
Jan. 23, 2001 |
| 6177360 |
Process for manufacture of integrated circuit device |
Jan. 23, 2001 |
| 6177352 |
Method for producing semiconductor bodies with an MOVPE layer sequence |
Jan. 23, 2001 |
| 6174823 |
Methods of forming a barrier layer |
Jan. 16, 2001 |
| 6171949 |
Low energy passivation of conductive material in damascene process for semiconductors |
Jan. 9, 2001 |
| 6165845 |
Method to fabricate poly tip in split-gate flash |
Dec. 26, 2000 |
| 6159833 |
Method of forming a contact hole in a semiconductor wafer |
Dec. 12, 2000 |
| 6156641 |
Semiconductor processing methods of forming self-aligned contact openings |
Dec. 5, 2000 |
| 6156217 |
Method for the purpose of producing a stencil mask |
Dec. 5, 2000 |
| 6153478 |
STI process for eliminating kink effect |
Nov. 28, 2000 |
| 6143649 |
Method for making semiconductor devices having gradual slope contacts |
Nov. 7, 2000 |
| 6140226 |
Dual damascene processing for semiconductor chip interconnects |
Oct. 31, 2000 |
| 6140677 |
Semiconductor topography for a high speed MOSFET having an ultra narrow gate |
Oct. 31, 2000 |
| 6133140 |
Method of manufacturing dual damascene utilizing anisotropic and isotropic properties |
Oct. 17, 2000 |
| 6127215 |
Deep pivot mask for enhanced buried-channel PFET performance and reliability |
Oct. 3, 2000 |
| 6117785 |
Multiple etch methods for forming contact holes in microelectronic devices including SOG layers and capping layers thereon |
Sep. 12, 2000 |
| 6114237 |
Method of forming contacts for a semiconductor device |
Sep. 5, 2000 |
| 6110833 |
Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation |
Aug. 29, 2000 |
| 6110824 |
Wire shape conferring reduced crosstalk and formation methods |
Aug. 29, 2000 |
| 6107158 |
Method of manufacturing a trench structure in a semiconductor substrate |
Aug. 22, 2000 |
| 6107138 |
Method for fabricating a semiconductor device having a tapered contact hole |
Aug. 22, 2000 |
| 6096651 |
Key-hole reduction during tungsten plug formation |
Aug. 1, 2000 |
| 6074951 |
Vapor phase etching of oxide masked by resist or masking material |
Jun. 13, 2000 |
| 6074942 |
Method for forming a dual damascene contact and interconnect |
Jun. 13, 2000 |
| 6057241 |
Method of manufacturing a semiconductor integrated circuit device |
May. 2, 2000 |
| 6045712 |
Micromachined reflector antenna method |
Apr. 4, 2000 |
| 6043151 |
Method for forming a semiconductor connection with a top surface having an enlarged recess |
Mar. 28, 2000 |
| 6040231 |
Method of fabricating a shallow trench isolation structure which includes using a salicide process to form an aslope periphery at the top corner of the substrate |
Mar. 21, 2000 |
