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Class Information
Number: 438/701
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Tapered configuration
Description: Processes wherein the viahole or trench is formed so as to possess nonparallel sides.


Patents under this class:
1 2 3 4 5 6 7 8 9 10

Patent Number Title Of Patent Date Issued
4445270 Low resistance contact for high density integrated circuit May. 1, 1984
4439270 Process for the controlled etching of tapered vias in borosilicate glass dielectrics Mar. 27, 1984
4420503 Low temperature elevated pressure glass flow/re-flow process Dec. 13, 1983
4411735 Polymeric insulation layer etching process and composition Oct. 25, 1983
4409319 Electron beam exposed positive resist mask process Oct. 11, 1983
4404733 Method of producing semiconductor devices Sep. 20, 1983
4390393 Method of forming an isolation trench in a semiconductor substrate Jun. 28, 1983
4389294 Method for avoiding residue on a vertical walled mesa Jun. 21, 1983
4389429 Method of forming integrated circuit chip transmission line Jun. 21, 1983
4363830 Method of forming tapered contact holes for integrated circuit devices Dec. 14, 1982
4356056 Process for insulating the interconnections of integrated circuits Oct. 26, 1982
4349584 Process for tapering openings in ternary glass coatings Sep. 14, 1982
4342617 Process for forming opening having tapered sides in a plasma nitride layer Aug. 3, 1982
4341010 Fabrication of electroluminescent semiconductor device utilizing selective etching and epitaxial deposition Jul. 27, 1982
4334349 Method of producing semiconductor device Jun. 15, 1982
4326771 Method of coupling between an optical fiber and an optoelectronic diode, and a transmitting or receiving head fabricated by means of said method Apr. 27, 1982
4307180 Process of forming recessed dielectric regions in a monocrystalline silicon substrate Dec. 22, 1981
4299862 Etching windows in thick dielectric coatings overlying semiconductor device surfaces Nov. 10, 1981
4286374 Large scale integrated circuit production Sep. 1, 1981
4284659 Insulation layer reflow Aug. 18, 1981
4279690 High-radiance emitters with integral microlens Jul. 21, 1981
4273805 Passivating composite for a semiconductor device comprising a silicon nitride (Si.sub.1 3N.sub.4) layer and phosphosilicate glass (PSG) layer Jun. 16, 1981
4256514 Method for forming a narrow dimensioned region on a body Mar. 17, 1981
4224089 Process for producing a semiconductor device Sep. 23, 1980
4218283 Method for fabricating semiconductor device and etchant for polymer resin Aug. 19, 1980
4210689 Method of producing semiconductor devices Jul. 1, 1980
4181564 Fabrication of patterned silicon nitride insulating layers having gently sloping sidewalls Jan. 1, 1980
4148133 Polysilicon mask for etching thick insulator Apr. 10, 1979
4104085 Method of manufacturing a semiconductor device by implanting ions through bevelled oxide layer in single masking step Aug. 1, 1978
4070501 Forming self-aligned via holes in thin film interconnection systems Jan. 24, 1978
4059480 Method of forming viaducts in semiconductor material Nov. 22, 1977
4052251 Method of etching sapphire utilizing sulfur hexafluoride Oct. 4, 1977
4040891 Etching process utilizing the same positive photoresist layer for two etching steps Aug. 9, 1977
4007104 Mesa fabrication process Feb. 8, 1977
3986200 Semiconductor structure and method Oct. 12, 1976
3980508 Process of producing semiconductor device Sep. 14, 1976
3958323 Three mask self aligned IGFET fabrication process May. 25, 1976
3947298 Method of forming junction regions utilizing R.F. sputtering Mar. 30, 1976
3945030 Semiconductor structure having contact openings with sloped side walls Mar. 16, 1976
3930305 Method for manufacturing integrated circuits Jan. 6, 1976

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