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Class Information
Number: 438/701
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench > Tapered configuration
Description: Processes wherein the viahole or trench is formed so as to possess nonparallel sides.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7365015 |
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1-xGe.sub.x as sacrificial material |
Apr. 29, 2008 |
| 7348202 |
CMOS image sensor and method for fabricating the same |
Mar. 25, 2008 |
| 7335593 |
Method of fabricating semiconductor device |
Feb. 26, 2008 |
| 7320927 |
In situ hardmask pullback using an in situ plasma resist trim process |
Jan. 22, 2008 |
| 7311850 |
Method of forming patterned thin film and method of fabricating micro device |
Dec. 25, 2007 |
| 7303648 |
Via etch process |
Dec. 4, 2007 |
| 7300882 |
Etching method and semiconductor device fabricating method |
Nov. 27, 2007 |
| 7297568 |
Three-dimensional structural body composed of silicon fine wire, its manufacturing method, and device using same |
Nov. 20, 2007 |
| 7282434 |
Method of manufacturing a semiconductor device |
Oct. 16, 2007 |
| 7271101 |
High density plasma chemical vapor deposition process |
Sep. 18, 2007 |
| 7259102 |
Etching technique to planarize a multi-layer structure |
Aug. 21, 2007 |
| 7255801 |
Deep submicron CMOS compatible suspending inductor |
Aug. 14, 2007 |
| 7241679 |
Method of manufacturing semiconductor device |
Jul. 10, 2007 |
| 7238609 |
Method for fabricating semiconductor device |
Jul. 3, 2007 |
| 7211517 |
Semiconductor device and method that includes reverse tapering multiple layers |
May. 1, 2007 |
| 7199053 |
Method for detecting end-point of chemical mechanical polishing process |
Apr. 3, 2007 |
| 7195927 |
Process for making magnetic memory structures having different-sized memory cell layers |
Mar. 27, 2007 |
| 7186650 |
Control of bottom dimension of tapered contact via variation(s) of etch process |
Mar. 6, 2007 |
| 7183217 |
Dry-etching method |
Feb. 27, 2007 |
| 7172971 |
Semiconductor device having a contact window including a lower with a wider to provide a lower contact resistance |
Feb. 6, 2007 |
| 7174072 |
Optical device having optical waveguide and method for manufacturing the same |
Feb. 6, 2007 |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
Jan. 30, 2007 |
| 7125791 |
Advanced copper damascene structure |
Oct. 24, 2006 |
| 7122476 |
Method for fabricating semiconductor device by forming trenches in different depths at a cellregion and a peripheral region for reducing self aligned source resistance at the cell region |
Oct. 17, 2006 |
| 7118933 |
Method for manufacturing optical bench, optical bench, optical module, silicon wafer substrate in which wiring and groove are formed, and wafer |
Oct. 10, 2006 |
| 7109120 |
Profiled standoff structure and method for optical display package |
Sep. 19, 2006 |
| 7098115 |
Semiconductor device and method of manufacturing the same |
Aug. 29, 2006 |
| 7084065 |
Method for fabricating a semiconductor device |
Aug. 1, 2006 |
| 7078279 |
Manufacturing method of a thin film transistor array substrate |
Jul. 18, 2006 |
| 7078346 |
High density plasma chemical vapor deposition process |
Jul. 18, 2006 |
| 7074725 |
Method for forming a storage node of a capacitor |
Jul. 11, 2006 |
| 7030008 |
Techniques for patterning features in semiconductor devices |
Apr. 18, 2006 |
| 7030444 |
Space process to prevent the reverse tunneling in split gate flash |
Apr. 18, 2006 |
| 7022602 |
Nitrogen-enriched low-k barrier layer for a copper metallization layer |
Apr. 4, 2006 |
| 7019400 |
Semiconductor device having multilayer interconnection structure and method for manufacturing the device |
Mar. 28, 2006 |
| 7015516 |
Led packages having improved light extraction |
Mar. 21, 2006 |
| 7001789 |
Method for fabricating a tapered optical coupling into a slab waveguide |
Feb. 21, 2006 |
| 6984858 |
Semiconductor device and manufacturing method thereof |
Jan. 10, 2006 |
| 6972235 |
Method for processing semiconductor substrate |
Dec. 6, 2005 |
| 6960530 |
Method of reducing the aspect ratio of a trench |
Nov. 1, 2005 |
| 6960522 |
Method for making damascene interconnect with bilayer capping film |
Nov. 1, 2005 |
| 6960514 |
Pitcher-shaped active area for field effect transistor and method of forming same |
Nov. 1, 2005 |
| 6929959 |
Manufacturing method of CPP type magnetic sensor having current-squeezing path |
Aug. 16, 2005 |
| 6924230 |
Method for forming a conductive layer |
Aug. 2, 2005 |
| 6905938 |
Method of forming interconnect structure with low dielectric constant |
Jun. 14, 2005 |
| 6893954 |
Method for patterning a semiconductor wafer |
May. 17, 2005 |
| 6892452 |
Method of forming a projection electrode |
May. 17, 2005 |
| 6890775 |
Yield based, in-line defect sampling method |
May. 10, 2005 |
| 6890846 |
Method for manufacturing semiconductor integrated circuit device |
May. 10, 2005 |
| 6886238 |
Method for manufacturing a head for recording and reading optical data |
May. 3, 2005 |
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