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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7049165 |
Method of manufacturing an external force detection sensor |
May. 23, 2006 |
| 7049239 |
STI structure and fabricating methods thereof |
May. 23, 2006 |
| 7045435 |
Shallow trench isolation method for a semiconductor wafer |
May. 16, 2006 |
| 7045450 |
Method of manufacturing semiconductor device |
May. 16, 2006 |
| 7042751 |
Method to produce data cell region and system region for semiconductor memory |
May. 9, 2006 |
| 7041567 |
Isolation structure for trench capacitors and fabrication method thereof |
May. 9, 2006 |
| 7041602 |
Method of fabricating semiconductor device |
May. 9, 2006 |
| 7037770 |
Method of manufacturing strained dislocation-free channels for CMOS |
May. 2, 2006 |
| 7037825 |
Damascene method capable of avoiding copper extrusion |
May. 2, 2006 |
| 7037841 |
Dual damascene interconnecting line structure and fabrication method thereof |
May. 2, 2006 |
| 7033944 |
Dual damascene process |
Apr. 25, 2006 |
| 7033945 |
Gap filling with a composite layer |
Apr. 25, 2006 |
| 7033946 |
Plasmaless dry contact cleaning method using interhalogen compounds |
Apr. 25, 2006 |
| 7033947 |
Dual trench alternating phase shift mask fabrication |
Apr. 25, 2006 |
| 7033955 |
Method for fabricating a semiconductor device |
Apr. 25, 2006 |
| 7029937 |
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Apr. 18, 2006 |
| 7029977 |
Fabrication method of semiconductor wafer |
Apr. 18, 2006 |
| 7030008 |
Techniques for patterning features in semiconductor devices |
Apr. 18, 2006 |
| 7030017 |
Method for the planarization of a semiconductor structure |
Apr. 18, 2006 |
| 7030022 |
Method of manufacturing semiconductor device having metal interconnections of different thickness |
Apr. 18, 2006 |
| 7030023 |
Method for simultaneous degas and baking in copper damascene process |
Apr. 18, 2006 |
| 7030044 |
Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
Apr. 18, 2006 |
| 7026172 |
Reduced thickness variation in a material layer deposited in narrow and wide integrated circuit trenches |
Apr. 11, 2006 |
| 7026248 |
Method for manufacturing semiconductor device with semiconductor region inserted into trench |
Apr. 11, 2006 |
| 7022609 |
Manufacturing method of a semiconductor substrate provided with a through hole electrode |
Apr. 4, 2006 |
| 7018552 |
Method of manufacturing electronic device |
Mar. 28, 2006 |
| 7018886 |
Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control |
Mar. 28, 2006 |
| 7018927 |
Method for forming isolation film for semiconductor devices |
Mar. 28, 2006 |
| 7015115 |
Method for forming deep trench isolation and related structure |
Mar. 21, 2006 |
| 7015134 |
Method for reducing anti-reflective coating layer removal during removal of photoresist |
Mar. 21, 2006 |
| 7015137 |
Semiconductor device with reduced interconnection capacity |
Mar. 21, 2006 |
| 7015145 |
Self-aligned collar and strap formation for semiconductor devices |
Mar. 21, 2006 |
| 7015147 |
Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si.sub.1-xGe.sub.x layer |
Mar. 21, 2006 |
| 7015516 |
Led packages having improved light extraction |
Mar. 21, 2006 |
| 7012007 |
Strained silicon MOSFET having improved thermal conductivity and method for its fabrication |
Mar. 14, 2006 |
| 7012022 |
Self-patterning of photo-active dielectric materials for interconnect isolation |
Mar. 14, 2006 |
| 7008849 |
Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts |
Mar. 7, 2006 |
| 7001836 |
Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers |
Feb. 21, 2006 |
| 6998313 |
Stacked gate flash memory device and method of fabricating the same |
Feb. 14, 2006 |
| 6994949 |
Method for manufacturing multi-level interconnections with dual damascene process |
Feb. 7, 2006 |
| 6995082 |
Bonding pad of a semiconductor device and formation method thereof |
Feb. 7, 2006 |
| 6995095 |
Methods of simultaneously fabricating isolation structures having varying dimensions |
Feb. 7, 2006 |
| 6992003 |
Integration of ultra low K dielectric in a semiconductor fabrication process |
Jan. 31, 2006 |
| 6992010 |
Gate structure and method of manufacture |
Jan. 31, 2006 |
| 6989282 |
Control of liner thickness for improving thermal cycle reliability |
Jan. 24, 2006 |
| 6987065 |
Method of manufacturing self aligned electrode with field insulation |
Jan. 17, 2006 |
| 6984858 |
Semiconductor device and manufacturing method thereof |
Jan. 10, 2006 |
| 6979652 |
Etching multi-shaped openings in silicon |
Dec. 27, 2005 |
| 6977203 |
Method of forming narrow trenches in semiconductor substrates |
Dec. 20, 2005 |
| 6977216 |
Method for forming metal wire in semiconductor device |
Dec. 20, 2005 |
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