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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7109080 |
Method of forming capacitor over bitline contact |
Sep. 19, 2006 |
| 7105445 |
Interconnect structures with encasing cap and methods of making thereof |
Sep. 12, 2006 |
| 7105453 |
Method for forming contact holes |
Sep. 12, 2006 |
| 7101802 |
Method for forming bottle-shaped trench |
Sep. 5, 2006 |
| 7101803 |
Method of trench isolation and method for manufacturing a non-volatile memory device using the same |
Sep. 5, 2006 |
| 7101804 |
Method for forming fuse integrated with dual damascene process |
Sep. 5, 2006 |
| 7101806 |
Deep trench formation in semiconductor device fabrication |
Sep. 5, 2006 |
| 7098135 |
Semiconductor device including bit line formed using damascene technique and method of fabricating the same |
Aug. 29, 2006 |
| 7098136 |
Structure having flush circuit features and method of making |
Aug. 29, 2006 |
| 7094629 |
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Aug. 22, 2006 |
| 7094697 |
Method for preparing a deep trench and an etching mixture for the same |
Aug. 22, 2006 |
| 7094701 |
Manufacturing method of semiconductor device |
Aug. 22, 2006 |
| 7094711 |
Micro pipe manufacturing method |
Aug. 22, 2006 |
| 7090786 |
Aqueous dispersion for chemical/mechanical polishing |
Aug. 15, 2006 |
| 7087498 |
Method for controlling trench depth in shallow trench isolation features |
Aug. 8, 2006 |
| 7087506 |
Method of forming freestanding semiconductor layer |
Aug. 8, 2006 |
| 7083994 |
Method of manufacturing a semiconductor device with outline of cleave marking regions and alignment or registration features |
Aug. 1, 2006 |
| 7084059 |
CMP system for metal deposition |
Aug. 1, 2006 |
| 7084065 |
Method for fabricating a semiconductor device |
Aug. 1, 2006 |
| 7081411 |
Wafer etching techniques |
Jul. 25, 2006 |
| 7081412 |
Double-sided etching technique for semiconductor structure with through-holes |
Jul. 25, 2006 |
| 7078296 |
Self-aligned trench MOSFETs and methods for making the same |
Jul. 18, 2006 |
| 7078314 |
Memory device having improved periphery and core isolation |
Jul. 18, 2006 |
| 7078334 |
In situ hard mask approach for self-aligned contact etch |
Jul. 18, 2006 |
| 7078346 |
High density plasma chemical vapor deposition process |
Jul. 18, 2006 |
| 7078348 |
Dual layer patterning scheme to make dual damascene |
Jul. 18, 2006 |
| 7078349 |
Method to form self-aligned floating gate to diffusion structures in flash |
Jul. 18, 2006 |
| 7074717 |
Damascene processes for forming conductive structures |
Jul. 11, 2006 |
| 7074718 |
Method of fabricating a semiconductor device having a buried and enlarged contact hole |
Jul. 11, 2006 |
| 7074723 |
Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system |
Jul. 11, 2006 |
| 7071072 |
Forming shallow trench isolation without the use of CMP |
Jul. 4, 2006 |
| 7071076 |
Method of manufacturing semiconductor device |
Jul. 4, 2006 |
| 7071107 |
Method for manufacturing a semiconductor device |
Jul. 4, 2006 |
| 7071108 |
Chemical mechanical polishing slurry containing abrasive particles exhibiting photocatalytic function |
Jul. 4, 2006 |
| 7071109 |
Methods for fabricating spatial light modulators with hidden comb actuators |
Jul. 4, 2006 |
| 7071112 |
BARC shaping for improved fabrication of dual damascene integrated circuit features |
Jul. 4, 2006 |
| 7071563 |
Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
Jul. 4, 2006 |
| 7067344 |
Method of manufacturing an external force detection sensor |
Jun. 27, 2006 |
| 7067440 |
Gap fill for high aspect ratio structures |
Jun. 27, 2006 |
| RE39143 |
Method for making a wafer-pair having sealed chambers |
Jun. 27, 2006 |
| 7064053 |
Process for fabricating an electrical circuit comprising a polishing step |
Jun. 20, 2006 |
| 7064072 |
Method for fabricating trench isolation |
Jun. 20, 2006 |
| 7064080 |
Semiconductor processing method using photoresist and an antireflective coating |
Jun. 20, 2006 |
| 7060624 |
Deep filled vias |
Jun. 13, 2006 |
| 7056830 |
Method for plasma etching a dielectric layer |
Jun. 6, 2006 |
| 7056832 |
Deep trench self-alignment process for an active area of a partial vertical cell |
Jun. 6, 2006 |
| 7052972 |
Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
May. 30, 2006 |
| 7049165 |
Method of manufacturing an external force detection sensor |
May. 23, 2006 |
| 7049239 |
STI structure and fabricating methods thereof |
May. 23, 2006 |
| 7045435 |
Shallow trench isolation method for a semiconductor wafer |
May. 16, 2006 |
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