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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6043160 |
Method of manufacturing a monitor pad for chemical mechanical polishing planarization |
Mar. 28, 2000 |
| 6036872 |
Method for making a wafer-pair having sealed chambers |
Mar. 14, 2000 |
| 6037221 |
Device and fabricating method of non-volatile memory |
Mar. 14, 2000 |
| 6037236 |
Regeneration of alignment marks after shallow trench isolation with chemical mechanical polishing |
Mar. 14, 2000 |
| 6037262 |
Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure |
Mar. 14, 2000 |
| 6037265 |
Etchant gas and a method for etching transistor gates |
Mar. 14, 2000 |
| 6033977 |
Dual damascene structure |
Mar. 7, 2000 |
| 6034416 |
Semiconductor device and method for fabricating the same |
Mar. 7, 2000 |
| 6030900 |
Process for generating a space in a structure |
Feb. 29, 2000 |
| 6027860 |
Method for forming a structure using redeposition of etchable layer |
Feb. 22, 2000 |
| 6028004 |
Process for controlling the height of a stud intersecting an interconnect |
Feb. 22, 2000 |
| 6025209 |
Deep groove structure for semiconductors |
Feb. 15, 2000 |
| 6025272 |
Method of planarize and improve the effectiveness of the stop layer |
Feb. 15, 2000 |
| 6020249 |
Method for photo alignment after CMP planarization |
Feb. 1, 2000 |
| 6020263 |
Method of recovering alignment marks after chemical mechanical polishing of tungsten |
Feb. 1, 2000 |
| 6020266 |
Single step electroplating process for interconnect via fill and metal line patterning |
Feb. 1, 2000 |
| 6020267 |
Method for forming local interconnect metal structures via the addition of a titanium nitride anti-reflective coating |
Feb. 1, 2000 |
| 6017817 |
Method of fabricating dual damascene |
Jan. 25, 2000 |
| 6015756 |
Trench-shaped read-only memory and its method of fabrication |
Jan. 18, 2000 |
| 6010962 |
Copper chemical-mechanical-polishing (CMP) dishing |
Jan. 4, 2000 |
| 6010965 |
Method of forming high integrity vias |
Jan. 4, 2000 |
| 6008123 |
Method for using a hardmask to form an opening in a semiconductor substrate |
Dec. 28, 1999 |
| 6008129 |
Process for forming a semiconductor device |
Dec. 28, 1999 |
| 6001699 |
Highly selective etch process for submicron contacts |
Dec. 14, 1999 |
| 5998263 |
High-density nonvolatile memory cell |
Dec. 7, 1999 |
| 5998300 |
Method of manufacturing a semiconductor device using antireflection coating |
Dec. 7, 1999 |
| 5998301 |
Method and system for providing tapered shallow trench isolation structure profile |
Dec. 7, 1999 |
| 5994229 |
Achievement of top rounding in shallow trench etch |
Nov. 30, 1999 |
| 5994762 |
Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof |
Nov. 30, 1999 |
| 5989977 |
Shallow trench isolation process |
Nov. 23, 1999 |
| 5990009 |
Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit |
Nov. 23, 1999 |
| 5985753 |
Method to manufacture dual damascene using a phantom implant mask |
Nov. 16, 1999 |
| 5985766 |
Semiconductor processing methods of forming a contact opening |
Nov. 16, 1999 |
| 5981388 |
Plasma CVD method for forming a semiconductor device having metal film formed thereby |
Nov. 9, 1999 |
| 5981993 |
Flash memory device and method of fabricating the same |
Nov. 9, 1999 |
| 5976968 |
Single-mask dual damascene processes by using phase-shifting mask |
Nov. 2, 1999 |
| 5976971 |
Fabrication process of a semiconductor device having an interconnection structure |
Nov. 2, 1999 |
| 5976984 |
Process of making unlanded vias |
Nov. 2, 1999 |
| 5972234 |
Debris-free wafer marking method |
Oct. 26, 1999 |
| 5968851 |
Controlled isotropic etch process and method of forming an opening in a dielectric layer |
Oct. 19, 1999 |
| 5970315 |
Microelectromechanical structure and process of making same |
Oct. 19, 1999 |
| 5966632 |
Method of forming borderless metal to contact structure |
Oct. 12, 1999 |
| 5962344 |
Plasma treatment method for PECVD silicon nitride films for improved passivation layers on semiconductor metal interconnections |
Oct. 5, 1999 |
| 5960321 |
Method of forming a contact via |
Sep. 28, 1999 |
| 5948703 |
Method of soft-landing gate etching to prevent gate oxide damage |
Sep. 7, 1999 |
| 5943571 |
Method for manufacturing fine structures |
Aug. 24, 1999 |
| 5939335 |
Method for reducing stress in the metallization of an integrated circuit |
Aug. 17, 1999 |
| 5933759 |
Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications |
Aug. 3, 1999 |
| 5928965 |
Method for dry-etching of silicon substrate |
Jul. 27, 1999 |
| 5930667 |
Method for fabricating multilevel interconnection structure for semiconductor devices |
Jul. 27, 1999 |
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