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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6287973 |
Method for forming interconnection structure |
Sep. 11, 2001 |
| 6284606 |
Process to achieve uniform groove depth in a silicon substrate |
Sep. 4, 2001 |
| 6281093 |
Method to reduce trench cone formation in the fabrication of shallow trench isolations |
Aug. 28, 2001 |
| 6281115 |
Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer |
Aug. 28, 2001 |
| 6277733 |
Oxygen-free, dry plasma process for polymer removal |
Aug. 21, 2001 |
| 6277752 |
Multiple etch method for forming residue free patterned hard mask layer |
Aug. 21, 2001 |
| 6277755 |
Method for fabricating an interconnect |
Aug. 21, 2001 |
| 6277756 |
Method for manufacturing semiconductor device |
Aug. 21, 2001 |
| 6274419 |
Trench isolation of field effect transistors |
Aug. 14, 2001 |
| 6274437 |
Trench gated power device fabrication by doping side walls of partially filled trench |
Aug. 14, 2001 |
| 6274482 |
Semiconductor processing methods of forming a contact opening |
Aug. 14, 2001 |
| 6274483 |
Method to improve metal line adhesion by trench corner shape modification |
Aug. 14, 2001 |
| 6274498 |
Methods of forming materials within openings, and method of forming isolation regions |
Aug. 14, 2001 |
| 6271070 |
Method of manufacturing semiconductor device |
Aug. 7, 2001 |
| 6271078 |
Simplifying conductive plate/via isolation |
Aug. 7, 2001 |
| 6271116 |
Method of fabricating interconnects |
Aug. 7, 2001 |
| 6271142 |
Process for manufacture of trench DRAM capacitor buried plates |
Aug. 7, 2001 |
| 6271143 |
Method for preventing trench fill erosion |
Aug. 7, 2001 |
| 6268283 |
Method for forming dual damascene structure |
Jul. 31, 2001 |
| 6268293 |
Method of forming wires on an integrated circuit chip |
Jul. 31, 2001 |
| 6265292 |
Method of fabrication of a novel flash integrated circuit |
Jul. 24, 2001 |
| 6265316 |
Etching method |
Jul. 24, 2001 |
| 6261921 |
Method of forming shallow trench isolation structure |
Jul. 17, 2001 |
| 6261962 |
Method of surface treatment of semiconductor substrates |
Jul. 17, 2001 |
| 6258729 |
Oxide etching method and structures resulting from same |
Jul. 10, 2001 |
| 6258732 |
Method of forming a patterned organic dielectric layer on a substrate |
Jul. 10, 2001 |
| 6255207 |
Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer |
Jul. 3, 2001 |
| 6255218 |
Semiconductor device and fabrication method thereof |
Jul. 3, 2001 |
| 6251774 |
Method of manufacturing a semiconductor device |
Jun. 26, 2001 |
| 6251791 |
Eliminating etching microloading effect by in situ deposition and etching |
Jun. 26, 2001 |
| 6248636 |
Method for forming contact holes of semiconductor memory device |
Jun. 19, 2001 |
| 6245640 |
Method for fabricating a semiconductor structure |
Jun. 12, 2001 |
| 6245656 |
Method for producing multi-level contacts |
Jun. 12, 2001 |
| 6242352 |
Method of preventing micro-scratches on the surface of a semiconductor wafer when performing a CMP process |
Jun. 5, 2001 |
| 6242357 |
Method for forming a deep trench capacitor of a DRAM cell |
Jun. 5, 2001 |
| 6242805 |
Method of using a polish stop film to control dishing during copper chemical mechanical polishing |
Jun. 5, 2001 |
| 6235628 |
Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer |
May. 22, 2001 |
| 6235637 |
Method for marking a wafer without inducing flat edge particle problem |
May. 22, 2001 |
| 6235642 |
Method for reducing plasma charging damages |
May. 22, 2001 |
| 6235645 |
Process for cleaning silicon semiconductor substrates |
May. 22, 2001 |
| 6232170 |
Method of fabricating trench for SOI merged logic DRAM |
May. 15, 2001 |
| 6232202 |
Method for manufacturing shallow trench isolation structure including a dual trench |
May. 15, 2001 |
| 6232231 |
Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect |
May. 15, 2001 |
| 6232232 |
High selectivity BPSG to TEOS etchant |
May. 15, 2001 |
| 6232243 |
Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps |
May. 15, 2001 |
| 6228768 |
Storage-annealing plated CU interconnects |
May. 8, 2001 |
| 6225207 |
Techniques for triple and quadruple damascene fabrication |
May. 1, 2001 |
| 6225217 |
Method of manufacturing semiconductor device having multilayer wiring |
May. 1, 2001 |
| 6225227 |
Method for manufacturing semiconductor device |
May. 1, 2001 |
| 6225230 |
Method of manufacturing semiconductor device |
May. 1, 2001 |
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