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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6617252 |
Monolithic low dielectric constant platform for passive components and method |
Sep. 9, 2003 |
| 6617257 |
Method of plasma etching organic antireflective coating |
Sep. 9, 2003 |
| 6613645 |
Method of manufacturing semiconductor device with glue layer in opening |
Sep. 2, 2003 |
| 6613666 |
Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures |
Sep. 2, 2003 |
| 6613679 |
Method for fabricating a semiconductor device |
Sep. 2, 2003 |
| 6613681 |
Method of removing etch residues |
Sep. 2, 2003 |
| 6610605 |
Method and apparatus for fabricating encapsulated micro-channels in a substrate |
Aug. 26, 2003 |
| 6607984 |
Removable inorganic anti-reflection coating process |
Aug. 19, 2003 |
| 6605541 |
Pitch reduction using a set of offset masks |
Aug. 12, 2003 |
| 6605542 |
Manufacturing method of semiconductor devices by using dry etching technology |
Aug. 12, 2003 |
| 6602791 |
Manufacture of integrated fluidic devices |
Aug. 5, 2003 |
| 6602794 |
Silylation process for forming contacts |
Aug. 5, 2003 |
| 6596607 |
Method of forming a trench type isolation layer |
Jul. 22, 2003 |
| 6596614 |
Use of membrane properties to reduce residual stress in an interlayer region |
Jul. 22, 2003 |
| 6596638 |
Polishing method |
Jul. 22, 2003 |
| 6593239 |
Chemical mechanical polishing method useful for copper substrates |
Jul. 15, 2003 |
| 6593242 |
Process for planarization and recess etching of integrated circuits |
Jul. 15, 2003 |
| 6589854 |
Method of forming shallow trench isolation |
Jul. 8, 2003 |
| 6589864 |
Method for defining windows with different etching depths simultaneously |
Jul. 8, 2003 |
| 6589870 |
Inter-layer connection structure, multilayer printed circuit board and production processes therefor |
Jul. 8, 2003 |
| 6589876 |
Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays |
Jul. 8, 2003 |
| 6590288 |
Selective deposition in integrated circuit interconnects |
Jul. 8, 2003 |
| 6586329 |
Semiconductor device and a method of manufacturing thereof |
Jul. 1, 2003 |
| 6583053 |
Use of a sacrificial layer to facilitate metallization for small features |
Jun. 24, 2003 |
| 6583060 |
Dual depth trench isolation |
Jun. 24, 2003 |
| 6583061 |
Method for creating an anti-blooming structure in a charge coupled device |
Jun. 24, 2003 |
| 6583062 |
Method of improving an aspect ratio while avoiding etch stop |
Jun. 24, 2003 |
| 6579801 |
Method for enhancing shallow trench top corner rounding using endpoint control of nitride layer etch process with appropriate etch front |
Jun. 17, 2003 |
| 6579808 |
Method of fabricating a semiconductor device |
Jun. 17, 2003 |
| 6576555 |
Method of making upper conductive line in dual damascene having lower copper lines |
Jun. 10, 2003 |
| 6576556 |
Method of manufacturing semiconductor device and method of manufacturing infrared image sensor |
Jun. 10, 2003 |
| 6576557 |
Semiconductor processing methods |
Jun. 10, 2003 |
| 6576558 |
High aspect ratio shallow trench using silicon implanted oxide |
Jun. 10, 2003 |
| 6573187 |
Method of forming dual damascene structure |
Jun. 3, 2003 |
| 6573188 |
End point detection method for forming a patterned silicon layer |
Jun. 3, 2003 |
| 6566230 |
Shallow trench isolation spacer for weff improvement |
May. 20, 2003 |
| 6566264 |
Method for forming an opening in a semiconductor device substrate |
May. 20, 2003 |
| 6562696 |
Method for forming an STI feature to avoid acidic etching of trench sidewalls |
May. 13, 2003 |
| 6562714 |
Consolidation method of junction contact etch for below 150 nanometer deep trench-based DRAM devices |
May. 13, 2003 |
| 6563148 |
Semiconductor device with dummy patterns |
May. 13, 2003 |
| 6559030 |
Method of forming a recessed polysilicon filled trench |
May. 6, 2003 |
| 6559049 |
All dual damascene oxide etch process steps in one confined plasma chamber |
May. 6, 2003 |
| 6555476 |
Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric |
Apr. 29, 2003 |
| 6555478 |
Stacked local interconnect structure and method of fabricating same |
Apr. 29, 2003 |
| 6551904 |
Method of manufacturing photodiodes |
Apr. 22, 2003 |
| 6551924 |
Post metalization chem-mech polishing dielectric etch |
Apr. 22, 2003 |
| 6551938 |
N2/H2 chemistry for dry development in top surface imaging technology |
Apr. 22, 2003 |
| 6548345 |
Method of fabricating trench for SOI merged logic DRAM |
Apr. 15, 2003 |
| 6548374 |
Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same |
Apr. 15, 2003 |
| 6548388 |
Semiconductor device including gate electrode having damascene structure and method of fabricating the same |
Apr. 15, 2003 |
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