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Class Information
Number: 438/700
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Formation of groove or trench
Description: Processes wherein at least one groove or trench is formed by a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6699794 |
Self aligned buried plate |
Mar. 2, 2004 |
| 6696344 |
Method for forming a bottle-shaped trench |
Feb. 24, 2004 |
| 6696366 |
Technique for etching a low capacitance dielectric layer |
Feb. 24, 2004 |
| 6693038 |
Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching |
Feb. 17, 2004 |
| 6693039 |
Process for forming a buried cavity in a semiconductor material wafer and a buried cavity |
Feb. 17, 2004 |
| 6693040 |
Method for cleaning the contact area of a metal line |
Feb. 17, 2004 |
| 6689683 |
Method of manufacturing a semiconductor device |
Feb. 10, 2004 |
| 6689695 |
Multi-purpose composite mask for dual damascene patterning |
Feb. 10, 2004 |
| 6686293 |
Method of etching a trench in a silicon-containing dielectric material |
Feb. 3, 2004 |
| 6679997 |
Organic insulation film formation method |
Jan. 20, 2004 |
| 6680247 |
Manufacturing method of a semiconductor device |
Jan. 20, 2004 |
| 6680248 |
Method of forming dual damascene structure |
Jan. 20, 2004 |
| 6680254 |
Method of fabricating bit line and bit line contact plug of a memory cell |
Jan. 20, 2004 |
| 6677240 |
Method for patterning dense and isolated features on semiconductor devices |
Jan. 13, 2004 |
| 6673694 |
Method for microfabricating structures using silicon-on-insulator material |
Jan. 6, 2004 |
| 6673704 |
Semiconductor device and method of manufacturing the same |
Jan. 6, 2004 |
| 6673720 |
Method for improving the reliability of flash memories |
Jan. 6, 2004 |
| 6670257 |
Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material |
Dec. 30, 2003 |
| 6670265 |
Low K dielectic etch in high density plasma etcher |
Dec. 30, 2003 |
| 6670267 |
Formation of tungstein-based interconnect using thin physically vapor deposited titanium nitride layer |
Dec. 30, 2003 |
| 6670275 |
Method of rounding a topcorner of trench |
Dec. 30, 2003 |
| 6663787 |
Use of ta/tan for preventing copper contamination of low-k dielectric layers |
Dec. 16, 2003 |
| 6664180 |
Method of forming smaller trench line width using a spacer hard mask |
Dec. 16, 2003 |
| 6664190 |
Pre STI-CMP planarization scheme |
Dec. 16, 2003 |
| 6664191 |
Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space |
Dec. 16, 2003 |
| 6660630 |
Method for forming a tapered dual damascene via portion with improved performance |
Dec. 9, 2003 |
| 6660636 |
Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating |
Dec. 9, 2003 |
| 6660642 |
Toxic residual gas removal by non-reactive ion sputtering |
Dec. 9, 2003 |
| 6656827 |
Electrical performance enhanced wafer level chip scale package with ground |
Dec. 2, 2003 |
| 6656843 |
Single mask trench fred with enlarged Schottky area |
Dec. 2, 2003 |
| 6656844 |
Method of forming a protected crown capacitor structure utilizing the outside crown surface to increase capacitance |
Dec. 2, 2003 |
| 6656845 |
Method for forming semiconductor substrate with convex shaped active region |
Dec. 2, 2003 |
| 6653237 |
High resist-selectivity etch for silicon trench etch applications |
Nov. 25, 2003 |
| 6653238 |
Method for forming semiconductor device having high-density contacts |
Nov. 25, 2003 |
| 6653241 |
Methods of forming protective segments of material, and etch stops |
Nov. 25, 2003 |
| 6649526 |
Method for implanting and coding a read-only memory with automatic alignment at four corners |
Nov. 18, 2003 |
| 6645867 |
Structure and method to preserve STI during etching |
Nov. 11, 2003 |
| 6645870 |
Process for fabricating semiconductor device |
Nov. 11, 2003 |
| 6642154 |
Method and apparatus for fabricating structures using chemically selective endpoint detection |
Nov. 4, 2003 |
| 6638871 |
Method for forming openings in low dielectric constant material layer |
Oct. 28, 2003 |
| 6635576 |
Method of fabricating borderless contact using graded-stair etch stop layers |
Oct. 21, 2003 |
| 6630389 |
Method for manufacturing semiconductor device |
Oct. 7, 2003 |
| 6627554 |
Semiconductor device manufacturing method |
Sep. 30, 2003 |
| 6620634 |
Method of accurately measuring compositions of thin film shape memory alloys |
Sep. 16, 2003 |
| 6620733 |
Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics |
Sep. 16, 2003 |
| 6620734 |
Methods of forming protective segments of material, and etch stops |
Sep. 16, 2003 |
| 6617232 |
Method of forming wiring using a dual damascene process |
Sep. 9, 2003 |
| 6617252 |
Monolithic low dielectric constant platform for passive components and method |
Sep. 9, 2003 |
| 6617257 |
Method of plasma etching organic antireflective coating |
Sep. 9, 2003 |
| 6613645 |
Method of manufacturing semiconductor device with glue layer in opening |
Sep. 2, 2003 |
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