| Patent Number |
Title Of Patent |
Date Issued |
| 6147001 |
Method of manufacturing semiconductor integrated circuit device |
Nov. 14, 2000 |
| 6140240 |
Method for eliminating CMP induced microscratches |
Oct. 31, 2000 |
| 6136716 |
Method for manufacturing a self-aligned stacked storage node DRAM cell |
Oct. 24, 2000 |
| 6127261 |
Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies |
Oct. 3, 2000 |
| 6114246 |
Method of using a polish stop film to control dishing during copper chemical mechanical polishing |
Sep. 5, 2000 |
| 6110827 |
Planarization method for self-aligned contact process |
Aug. 29, 2000 |
| 6103592 |
Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesa |
Aug. 15, 2000 |
| 6096654 |
Gapfill of semiconductor structure using doped silicate glasses |
Aug. 1, 2000 |
| 6083850 |
HSQ dielectric interlayer |
Jul. 4, 2000 |
| 6064466 |
Planarization method and system using variable exposure |
May. 16, 2000 |
| 6060393 |
Deposition control of stop layer and dielectric layer for use in the formation of local interconnects |
May. 9, 2000 |
| 6057242 |
Flat interlayer insulating film suitable for multi-layer wiring |
May. 2, 2000 |
| 6057211 |
Method for manufacturing an integrated circuit arrangement |
May. 2, 2000 |
| 6039851 |
Reactive sputter faceting of silicon dioxide to enhance gap fill of spaces between metal lines |
Mar. 21, 2000 |
| 6037251 |
Process for intermetal SOG/SOP dielectric planarization |
Mar. 14, 2000 |
| 6027950 |
Method for achieving accurate SOG etchback selectivity |
Feb. 22, 2000 |
| 6020266 |
Single step electroplating process for interconnect via fill and metal line patterning |
Feb. 1, 2000 |
| 6017144 |
Method and apparatus for depositing highly oriented and reflective crystalline layers using a low temperature seeding layer |
Jan. 25, 2000 |
| 6008068 |
Process for etching a semiconductor lead frame |
Dec. 28, 1999 |
| 5990000 |
Method and apparatus for improving gap-fill capability using chemical and physical etchbacks |
Nov. 23, 1999 |
| 5968844 |
Method for etching nitride features in integrated circuit construction |
Oct. 19, 1999 |
| 5963837 |
Method of planarizing the semiconductor structure |
Oct. 5, 1999 |
| 5958797 |
Planarization of a patterned structure on a substrate using an ion implantation-assisted wet chemical etch |
Sep. 28, 1999 |
| 5960321 |
Method of forming a contact via |
Sep. 28, 1999 |
| 5952243 |
Removal rate behavior of spin-on dielectrics with chemical mechanical polish |
Sep. 14, 1999 |
| 5950092 |
Use of a plasma source to form a layer during the formation of a semiconductor device |
Sep. 7, 1999 |
| 5940734 |
Method of fabricating a wiring on a planarized surface |
Aug. 17, 1999 |
| 5930677 |
Method for reducing microloading in an etchback of spin-on-glass or polymer |
Jul. 27, 1999 |
| 5916453 |
Methods of planarizing structures on wafers and substrates by polishing |
Jun. 29, 1999 |
| 5915201 |
Trench surrounded metal pattern |
Jun. 22, 1999 |
| 5914189 |
Protected thermal barrier coating composite with multiple coatings |
Jun. 22, 1999 |
| 5904558 |
Fabrication process of semiconductor device |
May. 18, 1999 |
| 5897371 |
Alignment process compatible with chemical mechanical polishing |
Apr. 27, 1999 |
| 5885894 |
Method of planarizing an inter-layer dielectric layer |
Mar. 23, 1999 |
| 5882990 |
Manufacturing method for wafer slice starting material to optimize extrinsic gettering during semiconductor fabrication |
Mar. 16, 1999 |
| 5880003 |
Method of giving a substantially flat surface of a semiconductor device through a polishing operation |
Mar. 9, 1999 |
| 5880026 |
Method for air gap formation by plasma treatment of aluminum interconnects |
Mar. 9, 1999 |
| 5872043 |
Method of planarizing wafers with shallow trench isolation |
Feb. 16, 1999 |
| 5863828 |
Trench planarization technique |
Jan. 26, 1999 |
| 5858860 |
Methods of fabricating field isolated semiconductor devices including step reducing regions |
Jan. 12, 1999 |
| 5858854 |
Method for forming high contrast alignment marks |
Jan. 12, 1999 |
| 5858870 |
Methods for gap fill and planarization of intermetal dielectrics |
Jan. 12, 1999 |
| 5854140 |
Method of making an aluminum contact |
Dec. 29, 1998 |
| 5854133 |
Method for manufacturing a semiconductor device |
Dec. 29, 1998 |
| 5850105 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish |
Dec. 15, 1998 |
| 5849637 |
Integration of spin-on gap filling dielectric with W-plug without outgassing |
Dec. 15, 1998 |
| 5833817 |
Method for improving conformity and contact bottom coverage of sputtered titanium nitride barrier layers |
Nov. 10, 1998 |
| 5830773 |
Method for forming semiconductor field region dielectrics having globally planarized upper surfaces |
Nov. 3, 1998 |
| 5821163 |
Method for achieving accurate SOG etchback selectivity |
Oct. 13, 1998 |
| 5817571 |
Multilayer interlevel dielectrics using phosphorus-doped glass |
Oct. 6, 1998 |
