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Class Information
Number: 438/697
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Planarization by etching and coating
Description: Processes wherein at least one surface of the semiconductor substrate is leveled through a combination of chemical etching and material deposition.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 4952274 |
Method for planarizing an insulating layer |
Aug. 28, 1990 |
| 4931144 |
Self-aligned nonnested sloped via |
Jun. 5, 1990 |
| 4874493 |
Method of deposition of metal into cavities on a substrate |
Oct. 17, 1989 |
| 4872947 |
CVD of silicon oxide using TEOS decomposition and in-situ planarization process |
Oct. 10, 1989 |
| 4824802 |
Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures |
Apr. 25, 1989 |
| 4818725 |
Technique for forming planarized gate structure |
Apr. 4, 1989 |
| 4789646 |
Method for selective surface treatment of semiconductor structures |
Dec. 6, 1988 |
| 4749663 |
Process of fabricating a semiconductor IC involving simultaneous sputter etching and deposition |
Jun. 7, 1988 |
| 4721548 |
Semiconductor planarization process |
Jan. 26, 1988 |
| 4710264 |
Process for manufacturing a semiconductor arrangement |
Dec. 1, 1987 |
| 4705596 |
Simultaneous plasma sculpturing and dual tapered aperture etch |
Nov. 10, 1987 |
| 4678538 |
Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects |
Jul. 7, 1987 |
| 4676868 |
Method for planarizing semiconductor substrates |
Jun. 30, 1987 |
| 4670091 |
Process for forming vias on integrated circuits |
Jun. 2, 1987 |
| 4665010 |
Method of fabricating photopolymer isolation trenches in the surface of a semiconductor wafer |
May. 12, 1987 |
| 4662064 |
Method of forming multi-level metallization |
May. 5, 1987 |
| 4655874 |
Process for smoothing a non-planar surface |
Apr. 7, 1987 |
| 4601781 |
Method for improving step coverage of dielectrics in VLSI circuits |
Jul. 22, 1986 |
| 4594769 |
Method of forming insulator of selectively varying thickness on patterned conductive layer |
Jun. 17, 1986 |
| 4520041 |
Method for forming metallization structure having flat surface on semiconductor substrate |
May. 28, 1985 |
| 4515652 |
Plasma sculpturing with a non-planar sacrificial layer |
May. 7, 1985 |
| 4511430 |
Control of etch rate ratio of SiO.sub.2 /photoresist for quartz planarization etch back process |
Apr. 16, 1985 |
| 4460434 |
Method for planarizing patterned surfaces |
Jul. 17, 1984 |
| 4362599 |
Method for making semiconductor device |
Dec. 7, 1982 |
| 4240095 |
Grooving and glassivating method for semiconductor wafers |
Dec. 16, 1980 |
| 4076573 |
Method of making planar silicon-on-sapphire composite |
Feb. 28, 1978 |
| 3990925 |
Removal of projections on epitaxial layers |
Nov. 9, 1976 |
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