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Class Information
Number: 438/697
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Planarization by etching and coating
Description: Processes wherein at least one surface of the semiconductor substrate is leveled through a combination of chemical etching and material deposition.

Sub-classes under this class:

Class Number Class Name Patents
438/699 Plural coating steps 453
438/698 Utilizing reflow 149

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
6858539 Post-CMP treating liquid and method for manufacturing semiconductor device Feb. 22, 2005
6858537 Process for smoothing a rough surface on a substrate by dry etching Feb. 22, 2005
6855585 Integrating multiple thin film resistors Feb. 15, 2005
6855634 Polishing method and polishing apparatus Feb. 15, 2005
6852634 Low cost method of providing a semiconductor device having a high channel density Feb. 8, 2005
6849551 Method for forming isolation region in semiconductor device Feb. 1, 2005
6849946 Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect Feb. 1, 2005
6828678 Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer Dec. 7, 2004
6828227 Method for applying uniform pressurized film across wafer Dec. 7, 2004
6827868 Thinning of fuse passivation after C4 formation Dec. 7, 2004
6821865 Deep isolation trenches Nov. 23, 2004
6821872 Method of making a bit line contact device Nov. 23, 2004
6821899 System, method and apparatus for improved local dual-damascene planarization Nov. 23, 2004
6818558 Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices Nov. 16, 2004
6815357 Process and apparatus for manufacturing a semiconductor device Nov. 9, 2004
6815336 Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing Nov. 9, 2004
6815334 Method for forming multi-layer metal line of semiconductor device Nov. 9, 2004
6815291 Method of manufacturing semiconductor device Nov. 9, 2004
6809033 Innovative method of hard mask removal Oct. 26, 2004
6809031 Method for manufacturing a reclaimable test pattern wafer for CMP applications Oct. 26, 2004
6809032 Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques Oct. 26, 2004
6803316 Method of planarizing by removing all or part of an oxidizable material layer from a semiconductor substrate Oct. 12, 2004
6800560 Gas assisted method for applying resist stripper and gas-resist stripper combinations Oct. 5, 2004
6797416 GaN substrate formed under controlled growth condition over GaN layer having discretely formed pits Sep. 28, 2004
6794691 Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features Sep. 21, 2004
6794261 Methods of forming void regions, dielectric regions and capacitor constructions Sep. 21, 2004
6790786 Etching processes for integrated circuit manufacturing including methods of forming capacitors Sep. 14, 2004
6780774 Method of semiconductor device isolation Aug. 24, 2004
6780753 Airgap for semiconductor devices Aug. 24, 2004
6774020 Semiconductor device and method of manufacturing the same Aug. 10, 2004
6774042 Planarization method for deep sub micron shallow trench isolation process Aug. 10, 2004
6767837 Etch-back method for dielectric layer Jul. 27, 2004
6753259 Method of improving the bondability between Au wires and Cu bonding pads Jun. 22, 2004
6750144 Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes Jun. 15, 2004
6746958 Method of controlling the duration of an endpoint polishing process in a multistage polishing process Jun. 8, 2004
6734106 Method of buried strap out-diffusion formation by gas phase doping May. 11, 2004
6730603 System and method of determining a polishing endpoint by monitoring signal intensity May. 4, 2004
6727158 Structure and method for forming a faceted opening and a layer filling therein Apr. 27, 2004
6723648 Fabricating ferroelectric memory device Apr. 20, 2004
6720265 Composition compatible with aluminum planarization and methods therefore Apr. 13, 2004
6716720 Method for filling depressions on a semiconductor wafer Apr. 6, 2004
6713396 Method of fabricating high density sub-lithographic features on a substrate Mar. 30, 2004
6713398 Method of planarizing polysillicon plug Mar. 30, 2004
6713394 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Mar. 30, 2004
6707134 Semiconductor structure having an improved pre-metal dielectric stack and method for forming the same Mar. 16, 2004
6703270 Method of manufacturing a semiconductor device Mar. 9, 2004
6703314 Method for fabricating semiconductor device Mar. 9, 2004
6696358 Viscous protective overlayers for planarization of integrated circuits Feb. 24, 2004
6677227 Method of forming patterned metalization on patterned semiconductor wafers Jan. 13, 2004
6667237 Method and apparatus for patterning fine dimensions Dec. 23, 2003

1 2 3 4 5 6 7 8 9 10 11

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