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Class Information
Number: 438/697
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Planarization by etching and coating
Description: Processes wherein at least one surface of the semiconductor substrate is leveled through a combination of chemical etching and material deposition.










Sub-classes under this class:

Class Number Class Name Patents
438/699 Plural coating steps 453
438/698 Utilizing reflow 149


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
4665010 Method of fabricating photopolymer isolation trenches in the surface of a semiconductor wafer May. 12, 1987
4662064 Method of forming multi-level metallization May. 5, 1987
4655874 Process for smoothing a non-planar surface Apr. 7, 1987
4601781 Method for improving step coverage of dielectrics in VLSI circuits Jul. 22, 1986
4594769 Method of forming insulator of selectively varying thickness on patterned conductive layer Jun. 17, 1986
4520041 Method for forming metallization structure having flat surface on semiconductor substrate May. 28, 1985
4515652 Plasma sculpturing with a non-planar sacrificial layer May. 7, 1985
4511430 Control of etch rate ratio of SiO.sub.2 /photoresist for quartz planarization etch back process Apr. 16, 1985
4460434 Method for planarizing patterned surfaces Jul. 17, 1984
4362599 Method for making semiconductor device Dec. 7, 1982
4240095 Grooving and glassivating method for semiconductor wafers Dec. 16, 1980
4076573 Method of making planar silicon-on-sapphire composite Feb. 28, 1978
3990925 Removal of projections on epitaxial layers Nov. 9, 1976

1 2 3 4 5 6 7 8 9 10 11










 
 
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