Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Engineering
Class Information
Number: 438/697
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Planarization by etching and coating
Description: Processes wherein at least one surface of the semiconductor substrate is leveled through a combination of chemical etching and material deposition.










Sub-classes under this class:

Class Number Class Name Patents
438/699 Plural coating steps 453
438/698 Utilizing reflow 149


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
5601687 Mask design Feb. 11, 1997
5575886 Method for fabricating semiconductor device with chemical-mechanical polishing process for planarization of interlayer insulation films Nov. 19, 1996
5567661 Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound Oct. 22, 1996
5567658 Method for minimizing peeling at the surface of spin-on glasses Oct. 22, 1996
5500077 Method of polishing/flattening diamond Mar. 19, 1996
5482900 Method for forming a metallurgy system having a dielectric layer that is planar and void free Jan. 9, 1996
5456797 Method of planarizing trench structures Oct. 10, 1995
5445998 Method for the global planarization of surfaces of semiconductor integrated circuits Aug. 29, 1995
5441094 Trench planarization techniques Aug. 15, 1995
5429988 Process for producing high density conductive lines Jul. 4, 1995
5413953 Method for planarizing an insulator on a semiconductor substrate using ion implantation May. 9, 1995
5399389 Method for locally and globally planarizing chemical vapor deposition of SiO.sub.2 layers onto structured silicon substrates Mar. 21, 1995
5385867 Method for forming a multi-layer metallic wiring structure Jan. 31, 1995
5378318 Planarization Jan. 3, 1995
5372673 Method for processing a layer of material while using insitu monitoring and control Dec. 13, 1994
5354706 Formation of uniform dimension conductive lines on a semiconductor wafer Oct. 11, 1994
5324689 Critical dimension control with a planarized underlayer Jun. 28, 1994
5320708 Dry etching method Jun. 14, 1994
5316980 Method of making a semiconductor device by dry etching process May. 31, 1994
5302551 Method for planarizing the surface of an integrated circuit over a metal interconnect layer Apr. 12, 1994
5290399 Surface planarizing methods for integrated circuit devices Mar. 1, 1994
5275977 Insulating film forming method for semiconductor device interconnection Jan. 4, 1994
5264074 Flattening method for interlayer insulating film Nov. 23, 1993
5256565 Electrochemical planarization Oct. 26, 1993
5212116 Method for forming planarized films by preferential etching of the center of a wafer May. 18, 1993
5139608 Method of planarizing a semiconductor device surface Aug. 18, 1992
5122473 Process for forming a field isolation structure and gate structures in integrated MISFET devices Jun. 16, 1992
5110410 Zinc sulfide planarization May. 5, 1992
5091048 Ion milling to obtain planarization Feb. 25, 1992
5084407 Method for planarizing isolated regions Jan. 28, 1992
5084130 Method for depositing material on depressions Jan. 28, 1992
5077238 Method of manufacturing a semiconductor device with a planar interlayer insulating film Dec. 31, 1991
5068207 Method for producing a planar surface in integrated circuit manufacturing Nov. 26, 1991
4988405 Fabrication of devices utilizing a wet etchback procedure Jan. 29, 1991
4985373 Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures Jan. 15, 1991
4983546 Method for curing spin-on-glass film by utilizing ultraviolet irradiation Jan. 8, 1991
4952274 Method for planarizing an insulating layer Aug. 28, 1990
4931144 Self-aligned nonnested sloped via Jun. 5, 1990
4874493 Method of deposition of metal into cavities on a substrate Oct. 17, 1989
4872947 CVD of silicon oxide using TEOS decomposition and in-situ planarization process Oct. 10, 1989
4824802 Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures Apr. 25, 1989
4818725 Technique for forming planarized gate structure Apr. 4, 1989
4789646 Method for selective surface treatment of semiconductor structures Dec. 6, 1988
4749663 Process of fabricating a semiconductor IC involving simultaneous sputter etching and deposition Jun. 7, 1988
4721548 Semiconductor planarization process Jan. 26, 1988
4710264 Process for manufacturing a semiconductor arrangement Dec. 1, 1987
4705596 Simultaneous plasma sculpturing and dual tapered aperture etch Nov. 10, 1987
4678538 Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects Jul. 7, 1987
4676868 Method for planarizing semiconductor substrates Jun. 30, 1987
4670091 Process for forming vias on integrated circuits Jun. 2, 1987

1 2 3 4 5 6 7 8 9 10 11










 
 
  Recently Added Patents
Metal foil laminate, substrate for mounting LED, and light source device
Method of measuring the flux of a soil gas
Epoxy composition for encapsulating an optical semiconductor element
Apparatus with a local timing circuit that generates a multi-phase timing signal for a digital signal processing circuit
Electronic device, communication control method of electronic device, and information terminal device
Moulded tie strips
Toy
  Randomly Featured Patents
Seed planter apparatus and method
Combined tape recorder and player or similar article
Semiconductor devices and method, including TGZM, of making same
Connection module for a submergible pumping system and method for pumping fluids using such a module
Stapedial prosthesis and method of implanting the same
Position sensor device for elevator car
Semiconductor converter
Sub-assembly for a motor vehicle dash board area
Compartmented thermoplastic pellets
Method of assembling electrical circuit to vehicle panel