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Class Information
Number: 438/696
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Coating of sidewall
Description: Processes wherein the chemical etching and material deposition is affected so that only vertically disposed surfaces remain coated with the deposited material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6579812 Method for removing residual polymer after the dry etching process and reducing oxide loss Jun. 17, 2003
6579808 Method of fabricating a semiconductor device Jun. 17, 2003
6551940 Undoped silicon dioxide as etch mask for patterning of doped silicon dioxide Apr. 22, 2003
6537902 Method of forming a via hole in a semiconductor device Mar. 25, 2003
6534409 Silicon oxide co-deposition/etching process Mar. 18, 2003
6531067 Method for forming contact hole Mar. 11, 2003
6531068 Method of anisotropic etching of silicon Mar. 11, 2003
6528372 Sidewall spacer definition of gates Mar. 4, 2003
6524963 Method to improve etching of organic-based, low dielectric constant materials Feb. 25, 2003
6521138 Method for measuring width of bottom under cut during etching process Feb. 18, 2003
6521538 Method of forming a trench with a rounded bottom in a semiconductor device Feb. 18, 2003
6514422 Simplified etching technique for producing multiple undercut profiles Feb. 4, 2003
6500765 Method for manufacturing dual-spacer structure Dec. 31, 2002
6498091 Method of using a barrier sputter reactor to remove an underlying barrier layer Dec. 24, 2002
6492275 Control of transistor performance through adjustment of spacer oxide profile with a wet etch Dec. 10, 2002
6489247 Copper etch using HCl and HBR chemistry Dec. 3, 2002
6486039 Method of fabricating a trench isolation structure having sidewall oxide layers with different thicknesses Nov. 26, 2002
6475891 Method of forming a pattern for a semiconductor device Nov. 5, 2002
6475901 Method for manufacturing semiconductor device having a multi-layer interconnection Nov. 5, 2002
6472324 Method of manufacturing trench type element isolation structure Oct. 29, 2002
6472328 Methods of forming an electrical contact to semiconductive material Oct. 29, 2002
6458615 Method of fabricating micromachined structures and devices formed therefrom Oct. 1, 2002
6432813 Semiconductor processing method of forming insulative material over conductive lines Aug. 13, 2002
6426528 Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby Jul. 30, 2002
6426011 Method of making a printed circuit board Jul. 30, 2002
6420270 Method of producing an etch pattern Jul. 16, 2002
6416933 Method to produce small space pattern using plasma polymerization layer Jul. 9, 2002
6410443 Method for removing semiconductor ARC using ARC CMP buffing Jun. 25, 2002
6403485 Method to form a low parasitic capacitance pseudo-SOI CMOS device Jun. 11, 2002
6391771 Integrated circuit interconnect lines having sidewall layers May. 21, 2002
6391782 Process for forming multiple active lines and gate-all-around MOSFET May. 21, 2002
6387820 BC13/AR chemistry for metal overetching on a high density plasma etcher May. 14, 2002
6387810 Method for homogenizing device parameters through photoresist planarization May. 14, 2002
6380088 Method to form a recessed source drain on a trench side wall with a replacement gate technique Apr. 30, 2002
6376382 Method for forming an opening Apr. 23, 2002
6372603 Photodiode with tightly-controlled junction profile for CMOS image sensor with STI process Apr. 16, 2002
6365451 Transistor and method Apr. 2, 2002
6362102 Method of forming top metal contact to antifuse Mar. 26, 2002
6352932 Methods of forming integrated circuitry and integrated circuitry structures Mar. 5, 2002
6350696 Spacer etch method for semiconductor device Feb. 26, 2002
6342450 Method of forming insulating spacers in DRAM chips Jan. 29, 2002
6335261 Directional CVD process with optimized etchback Jan. 1, 2002
6329686 Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby Dec. 11, 2001
6326270 Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines Dec. 4, 2001
6326312 Contact hole of semiconductor and its forming method Dec. 4, 2001
6316348 High selectivity Si-rich SiON etch-stop layer Nov. 13, 2001
6303429 Structure of a capacitor section of a dynamic random-access memory Oct. 16, 2001
6303491 Method for fabricating self-aligned contact hole Oct. 16, 2001
6300236 Copper stud structure with refractory metal liner Oct. 9, 2001
6299788 Silicon etching process Oct. 9, 2001

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