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Class Information
Number: 438/696
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Coating of sidewall
Description: Processes wherein the chemical etching and material deposition is affected so that only vertically disposed surfaces remain coated with the deposited material.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
7294580 Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition Nov. 13, 2007
7291563 Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate Nov. 6, 2007
7282450 Sidewall coverage for copper damascene filling Oct. 16, 2007
7276447 Plasma dielectric etch process including ex-situ backside polymer removal for low-dielectric constant material Oct. 2, 2007
7259098 Methods for fabricating semiconductor devices Aug. 21, 2007
7250371 Reduction of feature critical dimensions Jul. 31, 2007
7238619 Method for eliminating bridging defect in via first dual damascene process Jul. 3, 2007
7235489 Device and method to eliminate shorting induced by via to metal misalignment Jun. 26, 2007
7232762 Method for forming an improved low power SRAM contact Jun. 19, 2007
7226852 Preventing damage to low-k materials during resist stripping Jun. 5, 2007
7223657 Methods of fabricating flash memory devices with floating gates that have reduced seams May. 29, 2007
7217625 Method of fabricating a semiconductor device having a shallow source/drain region May. 15, 2007
7208418 Sealing sidewall pores in low-k dielectrics Apr. 24, 2007
7192871 Semiconductor device with a line and method of fabrication thereof Mar. 20, 2007
7189652 Selective oxidation of gate stack Mar. 13, 2007
7179757 Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials Feb. 20, 2007
7175777 Method of forming a sub-micron tip feature Feb. 13, 2007
7176137 Method for multiple spacer width control Feb. 13, 2007
7169669 Method of making thin silicon sheets for solar cells Jan. 30, 2007
7169677 Method for producing a spacer structure Jan. 30, 2007
7166232 Method for producing a solid body including a microstructure Jan. 23, 2007
7141514 Selective plasma re-oxidation process using pulsed RF source power Nov. 28, 2006
7141485 Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits Nov. 28, 2006
7132134 Staggered in-situ deposition and etching of a dielectric layer for HDP CVD Nov. 7, 2006
7132368 Method for repairing plasma damage after spacer formation for integrated circuit devices Nov. 7, 2006
7129176 Optical device having micro lens array and method for manufacturing the same Oct. 31, 2006
7125805 Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing Oct. 24, 2006
7112531 Silicon oxide co-deposition/etching process Sep. 26, 2006
7109080 Method of forming capacitor over bitline contact Sep. 19, 2006
7105451 Method for manufacturing semiconductor device Sep. 12, 2006
7078347 Method for forming MOS transistors with improved sidewall structures Jul. 18, 2006
7071108 Chemical mechanical polishing slurry containing abrasive particles exhibiting photocatalytic function Jul. 4, 2006
7071111 Sealed nitride layer for integrated circuits Jul. 4, 2006
7064071 Method of forming a conformal spacer adjacent to a gate electrode structure Jun. 20, 2006
7064022 Method of forming merged FET inverter/logic gate Jun. 20, 2006
7052617 Simplified etching technique for producing multiple undercut profiles May. 30, 2006
7045450 Method of manufacturing semiconductor device May. 16, 2006
7041601 Method of manufacturing metal gate MOSFET with strained channel May. 9, 2006
7033948 Method for reducing dimensions between patterns on a photoresist Apr. 25, 2006
7033944 Dual damascene process Apr. 25, 2006
7029937 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument Apr. 18, 2006
7030022 Method of manufacturing semiconductor device having metal interconnections of different thickness Apr. 18, 2006
7018551 Pull-back method of forming fins in FinFets Mar. 28, 2006
7005375 Method to avoid copper contamination of a via or dual damascene structure Feb. 28, 2006
7001784 Method to control spacer width Feb. 21, 2006
6998348 Method for manufacturing electronic circuits integrated on a semiconductor substrate Feb. 14, 2006
6984858 Semiconductor device and manufacturing method thereof Jan. 10, 2006
6967165 Method for fabricating multilayer interconnect and method for checking the same Nov. 22, 2005
6960529 Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition Nov. 1, 2005
6960530 Method of reducing the aspect ratio of a trench Nov. 1, 2005

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