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Class Information
Number: 438/696
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Coating of sidewall
Description: Processes wherein the chemical etching and material deposition is affected so that only vertically disposed surfaces remain coated with the deposited material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6818488 |
Process for making a gate for a short channel CMOS transistor structure |
Nov. 16, 2004 |
| 6815355 |
Method of integrating L-shaped spacers in a high performance CMOS process via use of an oxide-nitride-doped oxide spacer |
Nov. 9, 2004 |
| 6809004 |
Method of forming a shallow trench isolation |
Oct. 26, 2004 |
| 6802322 |
Method of fabricating a stringerless flash memory |
Oct. 12, 2004 |
| 6803321 |
Nitride spacer formation |
Oct. 12, 2004 |
| 6800557 |
Process for manufacturing semiconductor integrated circuit device |
Oct. 5, 2004 |
| 6797626 |
Method of polishing copper layer of substrate |
Sep. 28, 2004 |
| 6797188 |
Self-cleaning process for etching silicon-containing material |
Sep. 28, 2004 |
| 6790780 |
Fabrication of 3-D capacitor with dual damascene process |
Sep. 14, 2004 |
| 6784091 |
Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices |
Aug. 31, 2004 |
| 6780337 |
Method for trench etching |
Aug. 24, 2004 |
| 6780774 |
Method of semiconductor device isolation |
Aug. 24, 2004 |
| 6776851 |
In-situ cleaning of a polymer coated plasma processing chamber |
Aug. 17, 2004 |
| 6770575 |
Method for improving thermal stability of fluorinated amorphous carbon low dielectric constant materials |
Aug. 3, 2004 |
| 6756259 |
Gate insulating structure for power devices, and related manufacturing process |
Jun. 29, 2004 |
| 6753242 |
Integrated circuit device and method therefor |
Jun. 22, 2004 |
| 6750150 |
Method for reducing dimensions between patterns on a photoresist |
Jun. 15, 2004 |
| 6746945 |
Method of forming a via hole in a semiconductor device |
Jun. 8, 2004 |
| 6743686 |
Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication |
Jun. 1, 2004 |
| 6740595 |
Etch process for recessing polysilicon in trench structures |
May. 25, 2004 |
| 6737349 |
Method of forming a copper wiring in a semiconductor device |
May. 18, 2004 |
| 6737356 |
Method of fabricating a semiconductor work object |
May. 18, 2004 |
| 6734107 |
Pitch reduction in semiconductor fabrication |
May. 11, 2004 |
| 6734106 |
Method of buried strap out-diffusion formation by gas phase doping |
May. 11, 2004 |
| 6730605 |
Redistribution of copper deposited films |
May. 4, 2004 |
| 6727158 |
Structure and method for forming a faceted opening and a layer filling therein |
Apr. 27, 2004 |
| 6716710 |
Using a first liner layer as a spacer in a semiconductor device |
Apr. 6, 2004 |
| 6713396 |
Method of fabricating high density sub-lithographic features on a substrate |
Mar. 30, 2004 |
| 6713397 |
Manufacturing method of semiconductor device |
Mar. 30, 2004 |
| 6713357 |
Method to reduce parasitic capacitance of MOS transistors |
Mar. 30, 2004 |
| 6709608 |
Semiconductor processing component |
Mar. 23, 2004 |
| 6709982 |
Double spacer FinFET formation |
Mar. 23, 2004 |
| 6703311 |
Method for estimating capacitance of deep trench capacitors |
Mar. 9, 2004 |
| 6703312 |
Method of forming active devices of different gatelengths using lithographic printed gate images of same length |
Mar. 9, 2004 |
| 6699763 |
Disposable spacer technology for reduced cost CMOS processing |
Mar. 2, 2004 |
| 6699792 |
Polymer spacers for creating small geometry space and method of manufacture thereof |
Mar. 2, 2004 |
| 6699793 |
Semiconductor device having multi-layered spacer and method of manufacturing the same |
Mar. 2, 2004 |
| 6689654 |
Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad |
Feb. 10, 2004 |
| 6689694 |
Micromechanical system fabrication method using (111) single crystalline silicon |
Feb. 10, 2004 |
| 6686286 |
Method for forming a borderless contact of a semiconductor device |
Feb. 3, 2004 |
| 6686293 |
Method of etching a trench in a silicon-containing dielectric material |
Feb. 3, 2004 |
| 6673253 |
Method of fabricating integrated LC/ESI device using smile, latent masking, and delayed locos techniques. |
Jan. 6, 2004 |
| 6673694 |
Method for microfabricating structures using silicon-on-insulator material |
Jan. 6, 2004 |
| 6664156 |
Method for forming L-shaped spacers with precise width control |
Dec. 16, 2003 |
| 6653228 |
Method for preparing semiconductor including formation of contact hole using difluoromethane gas |
Nov. 25, 2003 |
| 6638441 |
Method for pitch reduction |
Oct. 28, 2003 |
| 6632745 |
Method of forming almost L-shaped spacer for improved ILD gap fill |
Oct. 14, 2003 |
| 6632741 |
Self-trimming method on looped patterns |
Oct. 14, 2003 |
| 6632718 |
Disposable spacer technology for reduced cost CMOS processing |
Oct. 14, 2003 |
| 6632716 |
Semiconductor device and manufacturing method thereof |
Oct. 14, 2003 |
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