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Class Information
Number: 438/696
Name: Semiconductor device manufacturing: process > Chemical etching > Combined with coating step > Coating of sidewall
Description: Processes wherein the chemical etching and material deposition is affected so that only vertically disposed surfaces remain coated with the deposited material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8709267 Double patterning method using tilt-angle deposition Apr. 29, 2014
8709947 Method for forming pattern Apr. 29, 2014
8691697 Self-aligned devices and methods of manufacture Apr. 8, 2014
8691698 Controlled gas mixing for smooth sidewall rapid alternating etch process Apr. 8, 2014
8691701 Strip with reduced low-K dielectric damage Apr. 8, 2014
8685859 Self-aligned semiconductor trench structures Apr. 1, 2014
8679981 Method for self-aligned doubled patterning lithography Mar. 25, 2014
8673785 Gas distribution system having fast gas switching capabilities Mar. 18, 2014
8671878 Profile and CD uniformity control by plasma oxidation treatment Mar. 18, 2014
8673778 Tungsten film forming method Mar. 18, 2014
8673165 Sidewall image transfer process with multiple critical dimensions Mar. 18, 2014
8669186 Methods of forming SRAM devices using sidewall image transfer techniques Mar. 11, 2014
8664120 Semiconductor device manufacturing method Mar. 4, 2014
8664102 Dual sidewall spacer for seam protection of a patterned structure Mar. 4, 2014
8642483 Substrate processing with shrink etching step Feb. 4, 2014
8629040 Methods for epitaxially growing active regions between STI regions Jan. 14, 2014
8629052 Methods of forming semiconductor devices having narrow conductive line patterns Jan. 14, 2014
8629064 Multiple patterning lithography using spacer and self-aligned assist patterns Jan. 14, 2014
8623770 Method for sidewall spacer line doubling using atomic layer deposition of a titanium oxide Jan. 7, 2014
8617975 Semiconductor processing methods Dec. 31, 2013
8614148 Methods for forming fine patterns of a semiconductor device Dec. 24, 2013
8609488 Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith Dec. 17, 2013
8609491 Method for fabricating semiconductor device with buried bit lines Dec. 17, 2013
8598037 Silicon etch with passivation using plasma enhanced oxidation Dec. 3, 2013
8574447 Inorganic rapid alternating process for silicon etch Nov. 5, 2013
8568598 Tip type probe manufacturing method, tip type probe and tip type probe manufacturing apparatus Oct. 29, 2013
8557662 Method for fabricating side contact in semiconductor device using double trench process Oct. 15, 2013
8557706 Substrate processing method Oct. 15, 2013
8557128 Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers Oct. 15, 2013
8546258 Method of fabricating metal contact using double patterning technology and device formed thereby Oct. 1, 2013
8546265 Method, apparatus and program for manufacturing silicon structure Oct. 1, 2013
8546218 Method for fabricating semiconductor device with buried word line Oct. 1, 2013
8530264 Methods for manufacturing arrays for CMOS imagers Sep. 10, 2013
8524605 Fabrication and mask design methods using spatial frequency sextupling technique Sep. 3, 2013
8525168 Integrated circuit (IC) test probe Sep. 3, 2013
8524604 Method for forming fine pattern of semiconductor device Sep. 3, 2013
8518828 Semiconductor device fabrication method Aug. 27, 2013
8513125 Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate Aug. 20, 2013
8513131 Fin field effect transistor with variable channel thickness for threshold voltage tuning Aug. 20, 2013
8513132 Method for fabricating metal pattern in semiconductor device Aug. 20, 2013
8507384 Method for selectively modifying spacing between pitch multiplied structures Aug. 13, 2013
8501607 FinFET alignment structures using a double trench flow Aug. 6, 2013
8501626 Methods for high temperature etching a high-K material gate structure Aug. 6, 2013
8501611 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls Aug. 6, 2013
8492282 Methods of forming a masking pattern for integrated circuits Jul. 23, 2013
8492227 Method of forming side wall spacers for a semiconductor device Jul. 23, 2013
8491804 Substrate processing method Jul. 23, 2013
8486752 Phase change memory device having dielectric layer for isolating contact structure formed by growth, semiconductor device having the same, and methods for manufacturing the devices Jul. 16, 2013
8486288 Pattern forming method Jul. 16, 2013
8486838 Method for forming a fine pattern using isotropic etching Jul. 16, 2013

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