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Class Information
Number: 438/675
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Selective deposition of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the selective deposition results in the deposited conductive material being recessed below the top surface of the substrate.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| RE40983 |
Method to plate C4 to copper stud |
Nov. 17, 2009 |
| 7618892 |
Via hole forming method |
Nov. 17, 2009 |
| 7615490 |
Method for fabricating landing plug of semiconductor device |
Nov. 10, 2009 |
| 7615448 |
Method of forming low resistance void-free contacts |
Nov. 10, 2009 |
| 7611986 |
Dual damascene patterning method |
Nov. 3, 2009 |
| 7608535 |
Method for forming metal contact in semiconductor device |
Oct. 27, 2009 |
| 7608538 |
Formation of vertical devices by electroplating |
Oct. 27, 2009 |
| 7605070 |
Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same |
Oct. 20, 2009 |
| 7601623 |
Method of manufacturing a semiconductor device with a gate electrode having a laminate structure |
Oct. 13, 2009 |
| 7598171 |
Method of manufacturing a semiconductor device |
Oct. 6, 2009 |
| 7585710 |
Methods of forming electronic devices having partially elevated source/drain structures |
Sep. 8, 2009 |
| 7576004 |
Semiconductor chip and method of manufacturing semiconductor chip |
Aug. 18, 2009 |
| 7576003 |
Dual liner capping layer interconnect structure and method |
Aug. 18, 2009 |
| 7566652 |
Electrically inactive via for electromigration reliability improvement |
Jul. 28, 2009 |
| 7563714 |
Low resistance and inductance backside through vias and methods of fabricating same |
Jul. 21, 2009 |
| 7560378 |
Method for manufacturing semiconductor device |
Jul. 14, 2009 |
| 7547628 |
Method for manufacturing capacitor |
Jun. 16, 2009 |
| 7537959 |
Chip stack package and manufacturing method thereof |
May. 26, 2009 |
| 7538029 |
Method of room temperature growth of SiO.sub.x on silicide as an etch stop layer for metal contact open of semiconductor devices |
May. 26, 2009 |
| 7528068 |
Method for manufacturing semiconductor device |
May. 5, 2009 |
| 7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner |
Apr. 28, 2009 |
| 7521806 |
Chip spanning connection |
Apr. 21, 2009 |
| 7514362 |
Integrated circuit including sub-lithographic structures |
Apr. 7, 2009 |
| 7507661 |
Method of forming narrowly spaced flash memory contact openings and lithography masks |
Mar. 24, 2009 |
| 7504287 |
Methods for fabricating an integrated circuit |
Mar. 17, 2009 |
| 7501342 |
Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same |
Mar. 10, 2009 |
| 7494922 |
Small electrode for phase change memories |
Feb. 24, 2009 |
| 7485577 |
Method of forming metal line stacking structure in semiconductor device |
Feb. 3, 2009 |
| 7485578 |
Semiconductor device |
Feb. 3, 2009 |
| 7482272 |
Through chip connection |
Jan. 27, 2009 |
| 7479452 |
Method of forming contact plugs |
Jan. 20, 2009 |
| 7476613 |
Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (SAC) process |
Jan. 13, 2009 |
| 7473577 |
Integrated chip carrier with compliant interconnect |
Jan. 6, 2009 |
| 7473641 |
Method for manufacturing a semiconductor device, method for manufacturing magnetic memory, and the magnetic memory thereof |
Jan. 6, 2009 |
| 7473986 |
Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof |
Jan. 6, 2009 |
| 7470620 |
Microcircuit fabrication and interconnection |
Dec. 30, 2008 |
| 7470619 |
Interconnect with high aspect ratio plugged vias |
Dec. 30, 2008 |
| 7470612 |
Method of forming metal wiring layer of semiconductor device |
Dec. 30, 2008 |
| 7470553 |
Built-in design edit structures |
Dec. 30, 2008 |
| 7465662 |
Method of making semiconductor device |
Dec. 16, 2008 |
| 7465663 |
Semiconductor device fabrication method |
Dec. 16, 2008 |
| 7459393 |
Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts |
Dec. 2, 2008 |
| 7456099 |
Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
Nov. 25, 2008 |
| 7453150 |
Three-dimensional face-to-face integration assembly |
Nov. 18, 2008 |
| 7452809 |
Fabrication method of packaging substrate and packaging method using the packaging substrate |
Nov. 18, 2008 |
| 7452808 |
Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding |
Nov. 18, 2008 |
| 7452801 |
Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same |
Nov. 18, 2008 |
| 7439177 |
Method of manufacturing semiconductor device for improving contact hole filling characteristics while reducing parasitic capacitance of inter-metal dielectric |
Oct. 21, 2008 |
| 7432199 |
Method of fabricating semiconductor device having reduced contact resistance |
Oct. 7, 2008 |
| 7425502 |
Minimizing resist poisoning in the manufacture of semiconductor devices |
Sep. 16, 2008 |
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