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Class Information
Number: 438/674
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Selective deposition of conductive layer
Description: Processes wherein the conductive material is deposited upon selected regions of the substrate.










Sub-classes under this class:

Class Number Class Name Patents
438/675 Plug formation (i.e., in viahole) 1,133
438/677 Pretreatment of surface to enhance or retard deposition 395
438/676 Utilizing electromagnetic or wave energy 190


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
8709943 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region Apr. 29, 2014
8691597 Method for manufacturing a semiconductor device including application of a plating voltage Apr. 8, 2014
8691678 Composition and method for alloy having improved stress relaxation resistance Apr. 8, 2014
8685850 System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections Apr. 1, 2014
8679974 Method for fabricating interconnecting lines inside via holes of semiconductor device Mar. 25, 2014
8673776 Method for manufacturing semiconductor device having interlayer dielectric layers and a gate contact Mar. 18, 2014
8664106 Method of manufacturing semiconductor device Mar. 4, 2014
8637400 Interconnect structures and methods for back end of the line integration Jan. 28, 2014
8637401 Methods and devices for high accuracy deposition on a continuously moving substrate Jan. 28, 2014
8623700 Inter-chip communication Jan. 7, 2014
8623706 Microelectronic package with terminals on dielectric mass Jan. 7, 2014
8617970 Method of manufacturing semiconductor device Dec. 31, 2013
8614142 Laminated structure, multilayer wiring board, active matrix substrate, image display apparatus, and method for manufacturing laminated structure Dec. 24, 2013
8609491 Method for fabricating semiconductor device with buried bit lines Dec. 17, 2013
8604604 Conductive interconnects Dec. 10, 2013
8603915 Multi-stage silicidation process Dec. 10, 2013
8592312 Method for depositing a conductive capping layer on metal lines Nov. 26, 2013
8586476 Fabrication method for circuit substrate having post-fed die side power supply connections Nov. 19, 2013
8586472 Conductive lines and pads and method of manufacturing thereof Nov. 19, 2013
8580685 Integrated circuit having interleaved gridded features, mask set, and method for printing Nov. 12, 2013
8575025 Templated circuitry fabrication Nov. 5, 2013
8567048 Method of manufacture of multi-layer wire structure Oct. 29, 2013
8569119 Method for producing semiconductor device and display device Oct. 29, 2013
8563433 Process to form via hole in semiconductor wafer Oct. 22, 2013
8551884 Method of manufacturing semiconductor device Oct. 8, 2013
8552565 Chip package and method for forming the same Oct. 8, 2013
8551883 Masking method Oct. 8, 2013
8546257 Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array Oct. 1, 2013
8546218 Method for fabricating semiconductor device with buried word line Oct. 1, 2013
8530312 Vertical devices and methods of forming Sep. 10, 2013
8530349 Methods for fabricating semiconductor devices including a seed generation accelerating layer Sep. 10, 2013
8524601 Method of manufacturing semiconductor device using Resolution Enhanced Lithography Assisted Chemical Shrinkage (RELACS) Sep. 3, 2013
8507390 Methods and devices for forming nanostructure monolayers and devices including such monolayers Aug. 13, 2013
8486833 Fabrication of conductive pathways, microcircuits and microstructures in microfluidic networks Jul. 16, 2013
8481431 Method for opening one-side contact region of vertical transistor and method for fabricating one-side junction region using the same Jul. 9, 2013
8481417 Semiconductor structures including tight pitch contacts and methods to form same Jul. 9, 2013
8476170 Method of forming pattern, method of manufacturing semiconductor device, and method of manufacturing template Jul. 2, 2013
8470709 Formation of metal-containing nano-particles for use as catalysts for carbon nanotube synthesis Jun. 25, 2013
8470711 Tone inversion with partial underlayer etch for semiconductor device formation Jun. 25, 2013
8466063 Integration of bottom-up metal film deposition Jun. 18, 2013
8461678 Structure with self aligned resist layer on an interconnect surface and method of making same Jun. 11, 2013
8461044 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region Jun. 11, 2013
8450217 Method for making holes using a fluid jet May. 28, 2013
8445378 Method of manufacturing a CMOS device including molecular storage elements in a via level May. 21, 2013
8435854 Top electrode templating for DRAM capacitor May. 7, 2013
8431474 Three dimensional multilayer circuit Apr. 30, 2013
8420978 High throughput, low cost dual-mode patterning method for large area substrates Apr. 16, 2013
8395257 Electronic module and method for producing an electric functional layer on a substrate by blowing powder particles of an electrically conductive material Mar. 12, 2013
8389406 Method of manufacturing semiconductor device Mar. 5, 2013
8372748 Method for forming semiconductor device Feb. 12, 2013

1 2 3 4 5 6 7 8 9 10 11










 
 
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