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Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.

Patents under this class:

Patent Number Title Of Patent Date Issued
6348411 Method of making a contact structure Feb. 19, 2002
6340636 Method for forming metal line in semiconductor device Jan. 22, 2002
6337216 Methods of forming ferroelectric memory cells Jan. 8, 2002
6337266 Small electrode for chalcogenide memories Jan. 8, 2002
6333219 Method for forming a polysilicon node in a semiconductor device Dec. 25, 2001
6331482 Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization Dec. 18, 2001
6329279 Method of fabricating metal interconnect structure having outer air spacer Dec. 11, 2001
6329282 Method of improving the texture of aluminum metallization for tungsten etch back processing Dec. 11, 2001
6329291 Method of forming a lower storage node of a capacitor for dynamic random access memory Dec. 11, 2001
6326297 Method of making a tungsten nitride barrier layer with improved adhesion and stability using a silicon layer Dec. 4, 2001
6326320 Method for forming oxide layer on conductor plug of trench structure Dec. 4, 2001
6323126 Tungsten formation process Nov. 27, 2001
6323558 Method for fabricating a contact of a semiconductor device Nov. 27, 2001
6319768 Method for fabricating capacitor in dram cell Nov. 20, 2001
6319823 Process for forming a borderless via in a semiconductor device Nov. 20, 2001
6312984 Semiconductor processing method of forming a contact pedestal of forming a storage node of a capacitor and integrated circuitry Nov. 6, 2001
6313029 Method for forming multi-layer interconnection of a semiconductor device Nov. 6, 2001
6313037 Semiconductor device and method for manufacturing the same Nov. 6, 2001
6309960 Method of fabricating a semiconductor device Oct. 30, 2001
6309961 Method of forming damascene wiring in a semiconductor device Oct. 30, 2001
6309970 Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface Oct. 30, 2001
6306759 Method for forming self-aligned contact with liner Oct. 23, 2001
6303431 Method of fabricating bit lines Oct. 16, 2001
6303480 Silicon layer to improve plug filling by CVD Oct. 16, 2001
6303486 Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal Oct. 16, 2001
6303497 Method of fabricating a contact window Oct. 16, 2001
6303505 Copper interconnect with improved electromigration resistance Oct. 16, 2001
6300237 Semiconductor integrated circuit device and method for making the same Oct. 9, 2001
6300242 Semiconductor device and method of fabricating the same Oct. 9, 2001
6297156 Method for enhanced filling of high aspect ratio dual damascene structures Oct. 2, 2001
6297157 Time ramped method for plating of high aspect ratio semiconductor vias and channels Oct. 2, 2001
6294451 Semiconductor device and method for manufacturing the same Sep. 25, 2001
6287964 Method for forming a metallization layer of a semiconductor device Sep. 11, 2001
6284646 Methods of forming smooth conductive layers for integrated circuit devices Sep. 4, 2001
6281115 Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer Aug. 28, 2001
6281121 Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal Aug. 28, 2001
6277729 Method of manufacturing transistor barrier layer Aug. 21, 2001
6277731 Method for forming a semiconductor connection with a top surface having an enlarged recess Aug. 21, 2001
6277739 Method of forming a barrier layer underlying a tungsten plug structure in a high aspect ratio contact hole Aug. 21, 2001
6277740 Integrated circuit trenched features and method of producing same Aug. 21, 2001
6277741 Method and planarizing polysilicon layer Aug. 21, 2001
6277742 Method of protecting tungsten plug from corroding Aug. 21, 2001
6274423 Etch process for aligning a capacitor structure and an adjacent contact corridor Aug. 14, 2001
6274471 Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique Aug. 14, 2001
6274480 Method of Fabricating semiconductor device Aug. 14, 2001
6271075 Method of manufacturing semiconductor device which can reduce manufacturing cost without dropping performance of logic mixed DRAM Aug. 7, 2001
6271123 Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG Aug. 7, 2001
6271127 Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials Aug. 7, 2001
6271129 Method for forming a gap filling refractory metal layer having reduced stress Aug. 7, 2001
6271135 Method for forming copper-containing metal studs Aug. 7, 2001

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