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Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6406998 Formation of silicided contact by ion implantation Jun. 18, 2002
6403465 Method to improve copper barrier properties Jun. 11, 2002
6403466 Post-CMP-Cu deposition and CMP to eliminate surface voids Jun. 11, 2002
6403474 Controlled anneal conductors for integrated circuit interconnects Jun. 11, 2002
6403478 Low pre-heat pressure CVD TiN process Jun. 11, 2002
6395628 Contact/via force fill techniques May. 28, 2002
6395629 Interconnect method and structure for semiconductor devices May. 28, 2002
6395633 Method of forming micro-via May. 28, 2002
6391711 Method of forming electrical connection between stack capacitor and node location of substrate May. 21, 2002
6391766 Method of making a slot via filled dual damascene structure with middle stop layer May. 21, 2002
6391771 Integrated circuit interconnect lines having sidewall layers May. 21, 2002
6391772 Method for forming interconnects in semiconductor device May. 21, 2002
6387759 Method of fabricating a semiconductor device May. 14, 2002
6387806 Filling an interconnect opening with different types of alloys to enhance interconnect reliability May. 14, 2002
6383912 Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics May. 7, 2002
6383914 Method of manufacturing an aluminum interconnect structure of a semiconductor device having <111> orientation May. 7, 2002
6383920 Process of enclosing via for improved reliability in dual damascene interconnects May. 7, 2002
6380069 Method of removing micro-scratch on metal layer Apr. 30, 2002
6380071 Method of fabricating semiconductor device Apr. 30, 2002
6380082 Method of fabricating Cu interconnects with reduced Cu contamination Apr. 30, 2002
6380084 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling Apr. 30, 2002
6376359 Method of manufacturing metallic interconnect Apr. 23, 2002
6372114 Method of forming a semiconductor device Apr. 16, 2002
6372629 Methods of fabricating buried digit lines and semiconductor devices including same Apr. 16, 2002
6372630 Semiconductor device and fabrication method thereof Apr. 16, 2002
6372631 Method of making a via filled dual damascene structure without middle stop layer Apr. 16, 2002
6372641 Method of forming self-aligned via structure Apr. 16, 2002
6368951 Semiconductor device manufacturing method and semiconductor device Apr. 9, 2002
6368952 Diffusion inhibited dielectric structure for diffusion enhanced conductor layer Apr. 9, 2002
6368953 Encapsulated metal structures for semiconductor devices and MIM capacitors including the same Apr. 9, 2002
6368964 Method for reducing resistance in a conductor Apr. 9, 2002
6365505 Method of making a slot via filled dual damascene structure with middle stop layer Apr. 2, 2002
6365510 Method for fabricating a contact layer Apr. 2, 2002
6365514 Two chamber metal reflow process Apr. 2, 2002
6362042 DRAM having a cup-shaped storage node electrode recessed within an insulating layer Mar. 26, 2002
6362092 Planarization method on a damascene structure Mar. 26, 2002
6358812 Methods of forming storage capacitors Mar. 19, 2002
6358839 Solution to black diamond film delamination problem Mar. 19, 2002
6359329 Embedded wiring structure and method for forming the same Mar. 19, 2002
6355563 Versatile copper-wiring layout design with low-k dielectric integration Mar. 12, 2002
6352896 Method of manufacturing DRAM capacitor Mar. 5, 2002
6352916 Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench Mar. 5, 2002
6352919 Method of fabricating a borderless via Mar. 5, 2002
6352920 Process of manufacturing semiconductor device Mar. 5, 2002
6352924 Rework method for wafers that trigger WCVD backside alarm Mar. 5, 2002
6350682 Method of fabricating dual damascene structure using a hard mask Feb. 26, 2002
6350687 Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film Feb. 26, 2002
6350688 Via RC improvement for copper damascene and beyond technology Feb. 26, 2002
6348408 Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same Feb. 19, 2002
6348410 Low temperature hillock suppression method in integrated circuit interconnects Feb. 19, 2002

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