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Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6573607 Semiconductor device and manufacturing method thereof Jun. 3, 2003
6566241 Method of forming metal contact in semiconductor device May. 20, 2003
6566242 Dual damascene copper interconnect to a damascene tungsten wiring level May. 20, 2003
6566248 Graphoepitaxial conductor cores in integrated circuit interconnects May. 20, 2003
6562711 Method of reducing capacitance of interconnect May. 13, 2003
6559044 Method for forming contacts May. 6, 2003
6559050 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices May. 6, 2003
6555463 Methods of fabricating buried digit lines Apr. 29, 2003
6555468 Method for forming trench including a first and a second layer of photoresist Apr. 29, 2003
6555471 Method of making a void-free aluminum film Apr. 29, 2003
6555481 Semiconductor device and its manufacture Apr. 29, 2003
6551876 Processing methods of forming an electrically conductive plug to a node location Apr. 22, 2003
6551914 Method of forming polish stop by plasma treatment for interconnection Apr. 22, 2003
6551920 Semiconductor device and fabrication method thereof Apr. 22, 2003
6548394 Method of forming contact plugs Apr. 15, 2003
6544891 Method to eliminate post-CMP copper flake defect Apr. 8, 2003
6544905 Metal gate trim process by using self assembled monolayers Apr. 8, 2003
6545358 Integrated circuits having plugs in conductive layers therein and related methods Apr. 8, 2003
6545362 Semiconductor device and method of manufacturing the same Apr. 8, 2003
6541281 Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same Apr. 1, 2003
6541314 Semiconductor device with SOI structure and method of manufacturing the same Apr. 1, 2003
6541372 Method for manufacturing a conductor structure for an integrated circuit Apr. 1, 2003
6537905 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug Mar. 25, 2003
6537908 Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask Mar. 25, 2003
6537913 Method of making a semiconductor device with aluminum capped copper interconnect pads Mar. 25, 2003
6534399 Dual damascene process using self-assembled monolayer Mar. 18, 2003
6531387 Polishing of conductive layers in fabrication of integrated circuits Mar. 11, 2003
6528327 Method for fabricating semiconductor memory device having a capacitor Mar. 4, 2003
6528369 Layer structure having contact hole and method of producing same Mar. 4, 2003
6528409 Interconnect structure formed in porous dielectric material with minimized degradation and electromigration Mar. 4, 2003
6528418 Manufacturing method for semiconductor device Mar. 4, 2003
6524957 Method of forming in-situ electroplated oxide passivating film for corrosion inhibition Feb. 25, 2003
6521508 Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process Feb. 18, 2003
6521522 Method for forming contact holes for metal interconnection in semiconductor devices Feb. 18, 2003
6521530 Composite interposer and method for producing a composite interposer Feb. 18, 2003
6521531 Method for selectively growing a conductive film to fill a contact hole Feb. 18, 2003
6521532 Method for making integrated circuit including interconnects with enhanced electromigration resistance Feb. 18, 2003
6517894 Method for plating a first layer on a substrate and a second layer on the first layer Feb. 11, 2003
6518167 Method of forming a metal or metal nitride interface layer between silicon nitride and copper Feb. 11, 2003
6518185 Integration scheme for non-feature-size dependent cu-alloy introduction Feb. 11, 2003
6514854 Method of producing semiconductor integrated circuit device having a plug Feb. 4, 2003
6514856 Method for forming multi-layered interconnect structure Feb. 4, 2003
6514874 Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features Feb. 4, 2003
6511879 Interconnect line selectively isolated from an underlying contact plug Jan. 28, 2003
6511908 Method of manufacturing a dual damascene structure using boron nitride as trench etching stop film Jan. 28, 2003
6509263 Method for fabricating a semiconductor memory device having polysilicon with an enhanced surface concentration and reduced contact resistance Jan. 21, 2003
6503827 Method of reducing planarization defects Jan. 7, 2003
6500751 Method of forming recessed thin film landing pad structure Dec. 31, 2002
6500766 Post-cleaning method of a via etching process Dec. 31, 2002
6497991 Method of producing a printed circuit board and mask for carrying out the same Dec. 24, 2002

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