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Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6686266 Method for forming a fuse in a semiconductor device Feb. 3, 2004
6686270 Dual damascene trench depth monitoring Feb. 3, 2004
6686278 Method for forming a plug metal layer Feb. 3, 2004
6686279 Method for reducing gouging during via formation Feb. 3, 2004
6683000 Semiconductor-device fabrication method Jan. 27, 2004
6683002 Method to create a copper diffusion deterrent interface Jan. 27, 2004
6680247 Manufacturing method of a semiconductor device Jan. 20, 2004
6677647 Electromigration characteristics of patterned metal features in semiconductor devices Jan. 13, 2004
6673712 Method of forming dual-implanted gate and structure formed by the same Jan. 6, 2004
6673715 Methods of forming conductive contacts Jan. 6, 2004
6653187 Semiconductor processing methods Nov. 25, 2003
6645846 Methods of forming conductive contacts to conductive structures Nov. 11, 2003
6642146 Method of depositing copper seed on semiconductor substrates Nov. 4, 2003
6638850 Method of fabricating a semiconductor device having a trench-gate structure Oct. 28, 2003
6638861 Method of eliminating voids in W plugs Oct. 28, 2003
6638775 Method for fabricating semiconductor memory device Oct. 28, 2003
6635536 Method for manufacturing semiconductor memory device Oct. 21, 2003
6635562 Methods and solutions for cleaning polished aluminum-containing layers Oct. 21, 2003
6635565 Method of cleaning a dual damascene structure Oct. 21, 2003
6630389 Method for manufacturing semiconductor device Oct. 7, 2003
6627493 Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure Sep. 30, 2003
6627537 Bit line and manufacturing method thereof Sep. 30, 2003
6623996 Method of measuring contact alignment in a semiconductor device including an integrated circuit Sep. 23, 2003
6620725 Reduction of Cu line damage by two-step CMP Sep. 16, 2003
6620731 Method for fabricating semiconductor components and interconnects with contacts on opposing sides Sep. 16, 2003
6610594 Locally increasing sidewall density by ion implantation Aug. 26, 2003
6607962 Globally planarized backend compatible thin film resistor contact/interconnect process Aug. 19, 2003
6607977 Method of depositing a diffusion barrier for copper interconnect applications Aug. 19, 2003
6602749 Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance Aug. 5, 2003
6602770 Silicon layer to improve plug filling by CVD Aug. 5, 2003
6599833 Method and article for filling apertures in a high performance electronic substrate Jul. 29, 2003
6600231 Functional device unit and method of producing the same Jul. 29, 2003
6596629 Method for forming wire in semiconductor device Jul. 22, 2003
6596632 Method for forming an integrated circuit interconnect using a dual poly process Jul. 22, 2003
6593235 Semiconductor device with a tapered hole formed using multiple layers with different etching rates Jul. 15, 2003
6589863 Semiconductor device and manufacturing method thereof Jul. 8, 2003
6589865 Low pressure, low temperature, semiconductor gap filling process Jul. 8, 2003
6582757 Method for tungsten deposition without fluorine-contaminated silicon substrate Jun. 24, 2003
6583046 Post-treatment of low-k dielectric for prevention of photoresist poisoning Jun. 24, 2003
6583049 Semiconductor integrated circuit device and method for making the same Jun. 24, 2003
6579795 Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability Jun. 17, 2003
6576526 Darc layer for MIM process integration Jun. 10, 2003
6576542 Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry Jun. 10, 2003
6576546 Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications Jun. 10, 2003
6576547 Residue-free contact openings and methods for fabricating same Jun. 10, 2003
6576550 `Via first` dual damascene process for copper metallization Jun. 10, 2003
6573174 Method for reducing surface defects of semiconductor substrates Jun. 3, 2003
6573607 Semiconductor device and manufacturing method thereof Jun. 3, 2003
6566241 Method of forming metal contact in semiconductor device May. 20, 2003
6566242 Dual damascene copper interconnect to a damascene tungsten wiring level May. 20, 2003

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