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Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6620725 Reduction of Cu line damage by two-step CMP Sep. 16, 2003
6620731 Method for fabricating semiconductor components and interconnects with contacts on opposing sides Sep. 16, 2003
6610594 Locally increasing sidewall density by ion implantation Aug. 26, 2003
6607962 Globally planarized backend compatible thin film resistor contact/interconnect process Aug. 19, 2003
6607977 Method of depositing a diffusion barrier for copper interconnect applications Aug. 19, 2003
6602749 Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance Aug. 5, 2003
6602770 Silicon layer to improve plug filling by CVD Aug. 5, 2003
6599833 Method and article for filling apertures in a high performance electronic substrate Jul. 29, 2003
6600231 Functional device unit and method of producing the same Jul. 29, 2003
6596629 Method for forming wire in semiconductor device Jul. 22, 2003
6596632 Method for forming an integrated circuit interconnect using a dual poly process Jul. 22, 2003
6593235 Semiconductor device with a tapered hole formed using multiple layers with different etching rates Jul. 15, 2003
6589863 Semiconductor device and manufacturing method thereof Jul. 8, 2003
6589865 Low pressure, low temperature, semiconductor gap filling process Jul. 8, 2003
6582757 Method for tungsten deposition without fluorine-contaminated silicon substrate Jun. 24, 2003
6583046 Post-treatment of low-k dielectric for prevention of photoresist poisoning Jun. 24, 2003
6583049 Semiconductor integrated circuit device and method for making the same Jun. 24, 2003
6579795 Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability Jun. 17, 2003
6576526 Darc layer for MIM process integration Jun. 10, 2003
6576542 Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry Jun. 10, 2003
6576546 Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications Jun. 10, 2003
6576547 Residue-free contact openings and methods for fabricating same Jun. 10, 2003
6576550 `Via first` dual damascene process for copper metallization Jun. 10, 2003
6573174 Method for reducing surface defects of semiconductor substrates Jun. 3, 2003
6573607 Semiconductor device and manufacturing method thereof Jun. 3, 2003
6566241 Method of forming metal contact in semiconductor device May. 20, 2003
6566242 Dual damascene copper interconnect to a damascene tungsten wiring level May. 20, 2003
6566248 Graphoepitaxial conductor cores in integrated circuit interconnects May. 20, 2003
6562711 Method of reducing capacitance of interconnect May. 13, 2003
6559044 Method for forming contacts May. 6, 2003
6559050 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices May. 6, 2003
6555463 Methods of fabricating buried digit lines Apr. 29, 2003
6555468 Method for forming trench including a first and a second layer of photoresist Apr. 29, 2003
6555471 Method of making a void-free aluminum film Apr. 29, 2003
6555481 Semiconductor device and its manufacture Apr. 29, 2003
6551876 Processing methods of forming an electrically conductive plug to a node location Apr. 22, 2003
6551914 Method of forming polish stop by plasma treatment for interconnection Apr. 22, 2003
6551920 Semiconductor device and fabrication method thereof Apr. 22, 2003
6548394 Method of forming contact plugs Apr. 15, 2003
6544891 Method to eliminate post-CMP copper flake defect Apr. 8, 2003
6544905 Metal gate trim process by using self assembled monolayers Apr. 8, 2003
6545358 Integrated circuits having plugs in conductive layers therein and related methods Apr. 8, 2003
6545362 Semiconductor device and method of manufacturing the same Apr. 8, 2003
6541281 Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same Apr. 1, 2003
6541314 Semiconductor device with SOI structure and method of manufacturing the same Apr. 1, 2003
6541372 Method for manufacturing a conductor structure for an integrated circuit Apr. 1, 2003
6537905 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug Mar. 25, 2003
6537908 Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask Mar. 25, 2003
6537913 Method of making a semiconductor device with aluminum capped copper interconnect pads Mar. 25, 2003
6534399 Dual damascene process using self-assembled monolayer Mar. 18, 2003

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