| |
 |
|
Class Information
Number: 438/672
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > And patterning of conductive layer > Plug formation (i.e., in viahole)
Description: Processes wherein the patterning step results in the remaining conductive material being recessed below the top surface of the substrate.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7071098 |
Methods of fabricating interconnects for semiconductor components including a through hole entirely through the component and forming a metal nitride including separate precursor cycles |
Jul. 4, 2006 |
| 7071101 |
Sacrificial TiN arc layer for increased pad etch throughput |
Jul. 4, 2006 |
| 7071104 |
Laser alignment target |
Jul. 4, 2006 |
| 7071563 |
Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
Jul. 4, 2006 |
| 7067417 |
Methods of removing resistive remnants from contact holes using silicidation |
Jun. 27, 2006 |
| 7064064 |
Copper recess process with application to selective capping and electroless plating |
Jun. 20, 2006 |
| RE39126 |
Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs |
Jun. 13, 2006 |
| 7056813 |
Methods of forming backside connections on a wafer stack |
Jun. 6, 2006 |
| 7052949 |
Method for forming bit line |
May. 30, 2006 |
| 7052989 |
Semiconductor device having opening and method of fabricating the same |
May. 30, 2006 |
| 7052990 |
Sealed pores in low-k material damascene conductive structures |
May. 30, 2006 |
| 7052992 |
Tungsten plug corrosion prevention method using ionized air |
May. 30, 2006 |
| 7052999 |
Method for fabricating semiconductor device |
May. 30, 2006 |
| 7049230 |
Method of forming a contact plug in a semiconductor device |
May. 23, 2006 |
| 7045379 |
Method of manufacturing surface shape recognition sensor |
May. 16, 2006 |
| 7041541 |
Method for producing a semiconductor component, and semiconductor component produced by the same |
May. 9, 2006 |
| 7041592 |
Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process |
May. 9, 2006 |
| 7041597 |
Semiconductor device having void free contact and method for fabricating the contact |
May. 9, 2006 |
| 7037825 |
Damascene method capable of avoiding copper extrusion |
May. 2, 2006 |
| 7038289 |
Deep insulating trench |
May. 2, 2006 |
| 7033929 |
Dual damascene interconnect structure with improved electro migration lifetimes |
Apr. 25, 2006 |
| 7033934 |
Method of production of semiconductor package |
Apr. 25, 2006 |
| 7030006 |
Method for forming contact hole and spacer of semiconductor device |
Apr. 18, 2006 |
| 7030016 |
Post ECP multi-step anneal/H2 treatment to reduce film impurity |
Apr. 18, 2006 |
| 7026236 |
Method of forming multilayer interconnection structure, method of manufacturing circuit board, and method of manufacturing device |
Apr. 11, 2006 |
| 7026239 |
Method for making an anisotropic conductive polymer film on a semiconductor wafer |
Apr. 11, 2006 |
| 7019402 |
Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor |
Mar. 28, 2006 |
| 7015110 |
Method and structure of manufacturing high capacitance metal on insulator capacitors in copper |
Mar. 21, 2006 |
| 7015133 |
Dual damascene structure formed of low-k dielectric materials |
Mar. 21, 2006 |
| 7015137 |
Semiconductor device with reduced interconnection capacity |
Mar. 21, 2006 |
| 7012002 |
Semiconductor memory device and method for fabricating the same |
Mar. 14, 2006 |
| 7012017 |
Partially etched dielectric film with conductive features |
Mar. 14, 2006 |
| 7005375 |
Method to avoid copper contamination of a via or dual damascene structure |
Feb. 28, 2006 |
| 6998338 |
Method of producing an integrated circuit configuration |
Feb. 14, 2006 |
| 6998344 |
Method for fabricating semiconductor components by forming conductive members using solder |
Feb. 14, 2006 |
| 6995085 |
Underlayer protection for the dual damascene etching |
Feb. 7, 2006 |
| 6991981 |
Processing methods of forming an electrically conductive plug to a node location |
Jan. 31, 2006 |
| 6989282 |
Control of liner thickness for improving thermal cycle reliability |
Jan. 24, 2006 |
| 6989313 |
Metal-insulator-metal capacitor and method for manufacturing the same |
Jan. 24, 2006 |
| 6984555 |
Device and method for inhibiting oxidation of contact plugs in ferroelectric capacitor devices |
Jan. 10, 2006 |
| 6979638 |
Conducting wire and contact opening forming method for reducing photoresist thickness and via resistance |
Dec. 27, 2005 |
| 6977197 |
Semiconductor devices having DRAM cells and methods of fabricating the same |
Dec. 20, 2005 |
| 6974771 |
Methods and apparatus for forming barrier layers in high aspect ratio vias |
Dec. 13, 2005 |
| 6974774 |
Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask |
Dec. 13, 2005 |
| 6969674 |
Structure and method for fine pitch flip chip substrate |
Nov. 29, 2005 |
| 6967152 |
Multilevel electronic circuit and method of making the same |
Nov. 22, 2005 |
| 6967161 |
Method and resulting structure for fabricating DRAM cell structure using oxide line spacer |
Nov. 22, 2005 |
| 6964874 |
Void formation monitoring in a damascene process |
Nov. 15, 2005 |
| 6964921 |
Method for forming bit line of flash device |
Nov. 15, 2005 |
| 6962867 |
Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof |
Nov. 8, 2005 |
|
|
|
