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Class Information
Number: 438/647
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Diverse conductors > Having electrically conductive polysilicon component
Description: Processes wherein one of the diverse conductive layers is polycrystalline silicon.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7595521 |
Terraced film stack |
Sep. 29, 2009 |
| 7531451 |
SIP semiconductor device and method for manufacturing the same |
May. 12, 2009 |
| 7524757 |
Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer |
Apr. 28, 2009 |
| 7442319 |
Poly etch without separate oxide decap |
Oct. 28, 2008 |
| 7427543 |
Method to improve drive current by increasing the effective area of an electrode |
Sep. 23, 2008 |
| 7351654 |
Semiconductor device and method for producing the same |
Apr. 1, 2008 |
| 7291527 |
Work function control of metals |
Nov. 6, 2007 |
| 7265038 |
Method for forming a multi-layer seed layer for improved Cu ECP |
Sep. 4, 2007 |
| 7245015 |
Display apparatus |
Jul. 17, 2007 |
| 7195995 |
Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device |
Mar. 27, 2007 |
| 7189641 |
Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers |
Mar. 13, 2007 |
| 7169696 |
Method for making a system for selecting one wire from a plurality of wires |
Jan. 30, 2007 |
| 7162796 |
Method of making an interposer with contact structures |
Jan. 16, 2007 |
| 7160801 |
Integrated circuit using a dual poly process |
Jan. 9, 2007 |
| 7144807 |
Low resistivity titanium silicide on heavily doped semiconductor |
Dec. 5, 2006 |
| 7067391 |
Method to form a metal silicide gate device |
Jun. 27, 2006 |
| 7026232 |
Systems and methods for low leakage strained-channel transistor |
Apr. 11, 2006 |
| 7012021 |
Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device |
Mar. 14, 2006 |
| 7005378 |
Processes for fabricating conductive patterns using nanolithography as a patterning tool |
Feb. 28, 2006 |
| 6979880 |
Scalable high performance antifuse structure and process |
Dec. 27, 2005 |
| 6969916 |
Substrate having built-in semiconductor apparatus and manufacturing method thereof |
Nov. 29, 2005 |
| 6962861 |
Method of forming a polysilicon layer comprising microcrystalline grains |
Nov. 8, 2005 |
| 6960500 |
Semiconductor device and method of manufacturing the same including forming metal silicide gate lines and source lines |
Nov. 1, 2005 |
| 6946336 |
Method of making a nanoscale electronic device |
Sep. 20, 2005 |
| 6943065 |
Scalable high performance antifuse structure and process |
Sep. 13, 2005 |
| 6930039 |
Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
Aug. 16, 2005 |
| 6916704 |
Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor |
Jul. 12, 2005 |
| 6888242 |
Color contacts for a semiconductor package |
May. 3, 2005 |
| 6879043 |
Electrode structure and method for fabricating the same |
Apr. 12, 2005 |
| 6872639 |
Fabrication of semiconductor devices with transition metal boride films as diffusion barriers |
Mar. 29, 2005 |
| 6869867 |
SEMICONDUCTOR DEVICE COMPRISING METAL SILICIDE FILMS FORMED TO COVER GATE ELECTRODE AND SOURCE-DRAIN DIFFUSION LAYERS AND METHOD OF MANUFACTURING THE SAME WHEREIN THE SILICIDE ON GATE IS THICK |
Mar. 22, 2005 |
| 6858529 |
Methods of forming contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus |
Feb. 22, 2005 |
| 6844255 |
Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
Jan. 18, 2005 |
| 6844259 |
Method for forming contact plug in semiconductor device |
Jan. 18, 2005 |
| 6821879 |
Copper interconnect by immersion/electroless plating in dual damascene process |
Nov. 23, 2004 |
| 6809021 |
Wiring line and manufacture process thereof and semiconductor device and manufacturing process thereof |
Oct. 26, 2004 |
| 6800550 |
Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon |
Oct. 5, 2004 |
| 6797557 |
Methods and systems for forming embedded DRAM for an MIM capacitor |
Sep. 28, 2004 |
| 6797558 |
Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer |
Sep. 28, 2004 |
| 6797611 |
Method of fabricating contact holes on a semiconductor chip |
Sep. 28, 2004 |
| 6764910 |
Structure of semiconductor device and method for manufacturing the same |
Jul. 20, 2004 |
| 6750125 |
Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby |
Jun. 15, 2004 |
| 6740573 |
Method for forming an integrated circuit interconnect using a dual poly process |
May. 25, 2004 |
| 6739953 |
Mechanical stress free processing method |
May. 25, 2004 |
| 6677211 |
Method for eliminating polysilicon residue |
Jan. 13, 2004 |
| 6635568 |
Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients |
Oct. 21, 2003 |
| 6605532 |
Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same |
Aug. 12, 2003 |
| 6605500 |
Assembly process |
Aug. 12, 2003 |
| 6605490 |
Semiconductor device and production process thereof |
Aug. 12, 2003 |
| 6586299 |
Mixed mode process |
Jul. 1, 2003 |
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