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Class Information
Number: 438/646
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Diverse conductors > Having planarization step > Utilizing reflow
Description: Processes wherein the planarization step is conducted by decreasing the viscosity of a layer and causing a leveling of the same by the viscous flow thereof.










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
6306756 Method for production of semiconductor device Oct. 23, 2001
6306761 Method of manufacturing semiconductor device Oct. 23, 2001
6271137 Method of producing an aluminum stacked contact/via for multilayer Aug. 7, 2001
6265310 Method of forming contact holes on a semiconductor surface Jul. 24, 2001
6228722 Method for fabricating self-aligned metal silcide May. 8, 2001
6187667 Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit Feb. 13, 2001
6177344 BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient Jan. 23, 2001
6174808 Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS Jan. 16, 2001
6156646 Method of manufacturing semiconductor devices Dec. 5, 2000
6096654 Gapfill of semiconductor structure using doped silicate glasses Aug. 1, 2000
6090701 Method for production of semiconductor device Jul. 18, 2000
6060386 Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices May. 9, 2000
6010958 Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects Jan. 4, 2000
5994206 Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method Nov. 30, 1999
5994213 Aluminum plug process Nov. 30, 1999
5981382 PVD deposition process for CVD aluminum liner processing Nov. 9, 1999
5960321 Method of forming a contact via Sep. 28, 1999
5950105 Completely buried contact holes and methods of forming same Sep. 7, 1999
5946591 Method of making a semiconductor device having a flat surface Aug. 31, 1999
5946596 Method for preventing polycide line deformation by polycide hardening Aug. 31, 1999
5930674 Semiconductor device with improved planarization properties Jul. 27, 1999
5926736 Low temperature aluminum reflow for multilevel metallization Jul. 20, 1999
5924006 Trench surrounded metal pattern Jul. 13, 1999
5918118 Dual deposition methods for forming contact metallizations, capacitors, and memory devices Jun. 29, 1999
5913146 Semiconductor device having aluminum contacts or vias and method of manufacture therefor Jun. 15, 1999
5895264 Method for forming stacked polysilicon Apr. 20, 1999
5880023 Process for formation of wiring layer in semiconductor device Mar. 9, 1999
5877084 Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction Mar. 2, 1999
5877087 Low temperature integrated metallization process and apparatus Mar. 2, 1999
5862057 Method and apparatus for tuning a process recipe to target dopant concentrations in a doped layer Jan. 19, 1999
5854125 Dummy fill patterns to improve interconnect planarity Dec. 29, 1998
5851917 Method for manufacturing a multi-layer wiring structure of a semiconductor device Dec. 22, 1998
5843837 Method of contact hole burying Dec. 1, 1998
5840619 Method of making a semiconductor device having a planarized surface Nov. 24, 1998
5837603 Planarization method by use of particle dispersion and subsequent thermal flow Nov. 17, 1998
5814556 Method of filling a contact hole in a semiconductor substrate with a metal Sep. 29, 1998
5716869 Method of forming a wiring layer of a semiconductor device using reflow process Feb. 10, 1998
5702983 Method for manufacturing a semiconductor device with a metallic interconnection layer Dec. 30, 1997
5693564 Conductor fill reflow with intermetallic compound wetting layer for semiconductor fabrication Dec. 2, 1997
5665659 Method for forming metal layer of a semiconductor device Sep. 9, 1997
5656556 Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures Aug. 12, 1997
5543357 Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring metal Aug. 6, 1996
5534463 Method for forming a wiring layer Jul. 9, 1996
5512512 Contact hole filling in a semiconductor device by irradiation with plasma of inert gas ions Apr. 30, 1996
5418187 Method for extending electrically conductive layer into electrically insulating layer May. 23, 1995
5147819 Semiconductor metallization method Sep. 15, 1992
5110759 Conductive plug forming method using laser planarization May. 5, 1992
5100834 Method of planarizing metal layer Mar. 31, 1992
5066611 Method for improving step coverage of a metallization layer on an integrated circuit by use of molybdenum as an anti-reflective coating Nov. 19, 1991
5032233 Method for improving step coverage of a metallization layer on an integrated circuit by use of a high melting point metal as an anti-reflective coating during laser planarization Jul. 16, 1991

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