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Class Information
Number: 438/646
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Diverse conductors > Having planarization step > Utilizing reflow
Description: Processes wherein the planarization step is conducted by decreasing the viscosity of a layer and causing a leveling of the same by the viscous flow thereof.










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8642458 Method of fabricating nonvolatile memory device Feb. 4, 2014
8148205 Method of electrically connecting a microelectronic component Apr. 3, 2012
8114711 Method of electrically connecting a microelectronic component Feb. 14, 2012
8003522 Method for forming trenches with wide upper portion and narrow lower portion Aug. 23, 2011
7897471 Method and apparatus to improve the reliability of the breakdown voltage in high voltage devices Mar. 1, 2011
7868360 Semiconductor device with heat-resistant gate Jan. 11, 2011
7829457 Protection of conductors from oxidation in deposition chambers Nov. 9, 2010
7768036 Integrated circuitry Aug. 3, 2010
7732334 Method for manufacturing semiconductor device Jun. 8, 2010
7601610 Method for manufacturing a high integration density power MOS device Oct. 13, 2009
7528424 Integrated circuitry May. 5, 2009
7510961 Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure Mar. 31, 2009
7446399 Pad structures to improve board-level reliability of solder-on-pad BGA structures Nov. 4, 2008
7432184 Integrated PVD system using designated PVD chambers Oct. 7, 2008
7316974 Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device Jan. 8, 2008
7265044 Method for forming bump on electrode pad with use of double-layered film Sep. 4, 2007
7253409 Electrochemical nano-patterning using ionic conductors Aug. 7, 2007
7232762 Method for forming an improved low power SRAM contact Jun. 19, 2007
7199043 Method of forming copper wiring in semiconductor device Apr. 3, 2007
7172962 Method of manufacturing a semiconductor device Feb. 6, 2007
7166533 Phase change memory cell defined by a pattern shrink material process Jan. 23, 2007
7125800 Methods for making nearly planar dielectric films in integrated circuits Oct. 24, 2006
7067412 Semiconductor device and method of manufacturing the same Jun. 27, 2006
7005378 Processes for fabricating conductive patterns using nanolithography as a patterning tool Feb. 28, 2006
6969301 Filling plugs through chemical mechanical polish Nov. 29, 2005
6900121 Laser thermal annealing to eliminate oxide voiding May. 31, 2005
6888242 Color contacts for a semiconductor package May. 3, 2005
6812136 Method of making a semiconductor device having a multilayer metal film of titanium/titanium nitride/tungsten/tungsten carbide Nov. 2, 2004
6803308 Method of forming a dual damascene pattern in a semiconductor device Oct. 12, 2004
6787468 Method of fabricating metal lines in a semiconductor device Sep. 7, 2004
6720253 Method of manufacturing semiconductor device having an aluminum wiring layer Apr. 13, 2004
6696360 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Feb. 24, 2004
6673718 Methods for forming aluminum metal wirings Jan. 6, 2004
6639285 Method for fabricating a semiconductor device Oct. 28, 2003
6627541 Reflow method for construction of conductive vias Sep. 30, 2003
6627549 Methods for making nearly planar dielectric films in integrated circuits Sep. 30, 2003
6620534 Film having enhanced reflow characteristics at low thermal budget Sep. 16, 2003
6599828 Copper reflow process Jul. 29, 2003
6594894 Planar-processing compatible metallic micro-extrusion process Jul. 22, 2003
6566259 Integrated deposition process for copper metallization May. 20, 2003
6534398 Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit Mar. 18, 2003
6534396 Patterned conductor layer pasivation method with dimensionally stabilized planarization Mar. 18, 2003
6514876 Pre-metal dielectric rapid thermal processing for sub-micron technology Feb. 4, 2003
6475903 Copper reflow process Nov. 5, 2002
6475900 Method for manufacturing a metal interconnection having enhanced filling capability Nov. 5, 2002
6451684 Semiconductor device having a conductive layer side surface slope which is at least 90.degree. and method for manufacturing the same Sep. 17, 2002
6440841 Method of fabricating vias Aug. 27, 2002
6399486 Method of improved copper gap fill Jun. 4, 2002
6368956 Method of manufacturing a semiconductor device Apr. 9, 2002
6340641 Substrate flattening method and film-coated substrate made thereby Jan. 22, 2002

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